Coded data generation or conversion – Converter compensation
Reexamination Certificate
2002-06-05
2003-11-25
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000, C341S143000
Reexamination Certificate
active
06653958
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a method and a system for compensating the non-linearity of a sigma-delta analog-to-digital converter.
2. Description of the Related Art
Equipment in all fields, electronic or otherwise, consumer or professional, increasingly employs digital rather than analog processing. This choice is often justified by technical advantages that are now well known, such as very stable parameters, excellent reproducibility of results, and increased functionality.
The external world being inherently analog, in most cases analog-to-digital converters (ADC) and digital-to-analog converters (DAC) provide at some level the interface between the external world and the digital core of the equipment.
The development of powerful digital processors has created a need for a high-resolution analog-to-digital converter compatible with CMOS VLSI (Very Large Scale Integration) technologies. The sigma-delta modulation converter in particular has exploited technological developments.
As shown in
FIG. 1
, a sigma-delta analog-to-digital converter primarily includes an adder
1
, a noise-shaping filter
4
, a quantizer
5
, a digital filter
6
and a feedback loop
8
connecting the output of the quantizer
5
to the negative input
3
of the adder
1
. The feedback loop
8
includes an analog-to-digital converter
7
. A sample-and-hold device (not shown), usually on the input side of the adder
1
, oversamples the signal at a given frequency and then maintains the level at the output
2
constant to enable the sigma-delta analog-to-digital converter to process the data. The noise-shaping filter
4
shapes the noise spectrum to attenuate the noise power in the frequency range of the wanted signal. The quantizer
5
employs a set of discrete levels and associates the closest discrete level with the analog value at its input. This introduces an error known as “quantizing noise”. The performance of a converter is conditioned by the quantizing noise power. To this end, the oversampling performed in the sample-and-hold device (not shown) and the feedback loop
8
“pushes” the maximum quantizing noise power out of the pass-band of the signal (the band of frequencies at which the system operates). The digital filter
6
at the output of the sigma-delta analog-to-digital converter, also known as a decimation filter, eliminates the shaped quantizing noise and undersamples the output signal. The digital-to-analog converter
7
has a transfer function that links the input (quantizing) digital levels delivered by the quantizer
5
to output analog values that are then fed to the negative input
3
of the adder
1
. The analog-to-digital converter
7
associates a corresponding analog output value with each quantizing input level.
The fundamental principle of the sigma-delta analog-to-digital converter consists firstly of oversampling the signal using the analog sample-and-hold device, pushing the quantizing noise power maximum outside the pass-band of the signal, by integrating the quantizer into a feedback loop, and then filtering the signal obtained by means of a digital filter
6
. These conjugate actions initially “dilute” the quantizing noise in a wide band thanks to the oversampling, shape the noise spectrum, and then filter the quantizing noise to retain only the wanted band of the signal.
Using a multibit quantizer associated with a multibit digital-to-analog converter in the feedback loop of a sigma-delta analog-to-digital converter is beneficial because it improves the signal
oise ratio and dynamic range of the sigma-delta analog-to-digital converter.
However, the performance of the sigma-delta analog-to-digital converter is highly dependent on the linearity of the sigma-delta analog-to-digital converter
7
used in the feedback loop
8
.
One prior art solution that has been proposed for calibrating the multibit digital-to-analog converter regardless of the number of levels is described by SARHANG-NEJAD and G. C. TEMES, “A High Resolution Multibit Sigma Delta ADC with Digital Correction and Relaxed Amplifier Requirements”, IEEE Journal of solid state circuits, vol. 28, N 6, June 1993, pages 648-660. It proposes to improve the performance of the sigma-delta analog-to-digital converter by measuring the non-linearities of the digital-to-analog converter
7
during a calibration phase. During the calibration phase, the multibit sigma-delta analog-to-digital converter is converted into a one-bit sigma-delta analog-to-digital converter (only the most significant bit at the output of the quantizer is considered). The calibration phase essentially employs the components shown in
FIG. 2
, which shows the adder
1
, the noise-shaping filter
4
, the quantizer
5
and the decimation filter
6
. The digital-to-analog converter
7
is replaced by switching means Ea for imposing at the negative input
3
of the adder
1
either a positive voltage Vref or a negative voltage −Vref, depending on the value of the output of the one-bit quantizer
5
. The digital-to-analog converter
7
is then placed at the positive input
2
of the adder
1
. A counter Eb controls the digital-to-analog converter
7
by feeding it a digital signal (corresponding to one of the levels available to the quantizer
5
) so that it generates an analog signal at the input of the one-bit sigma-delta analog-to-digital converter. An adder Ec receiving the output signal of the counter Eb and the output signal of the decimation filter
6
calculates a correction value that is stored in a memory module Ed. The counter Eb also controls addressing of the memory module Ed.
Each correction value represents a digital error caused by the digital-to-analog converter
7
in converting between a digital value and its analog conversion. During the phase of normal use, the sigma-delta analog-to-digital converter is equivalent to that shown in
FIG. 1
with a digital correction module (not shown) containing the correction values added in front of the decimation filter
6
. All digital values leaving the quantizer
5
are corrected by the digital correction module before reaching the decimation filter
6
. Thus the corrected digital value entering the decimation filter
6
is substantially equal to the analog value at the negative input
3
of the adder
1
.
The above technique has a number of drawbacks, associated with the manner in which the correction values are measured. In the calibration phase (FIG.
2
), the output of the digital-to-analog converter
7
is fed to the positive input
2
of the adder
1
, whereas under normal operating conditions (
FIG. 1
plus correction module) the digital-to-analog converter
7
is in the feedback loop
8
and its output is fed to the negative input
3
of the adder
1
. The behavior of the digital-to-analog converter
7
differs between the calibration phase and normal operating conditions because the two inputs of the adder
1
are different. The two inputs of the adder
1
do not have exactly the same capacitance, because it generally uses switched capacitors.
FIG. 3
shows an adder using switched capacitors. The switches
9
,
10
and
12
,
13
respectively switch a capacitor C
1
and a capacitor C
2
which are connected to a ground
14
. The adder has two inputs E
1
and E
2
respectively connected to the capacitors C
1
and C
2
. An operational amplifier
11
performs the addition operation by means of a feedback capacitor C. The capacitors C
1
and C
2
theoretically have the same capacitance. However, in practice, because of manufacturing tolerances, their capacitances are different and the gain between the two inputs is therefore different.
During the calibration phase, the digital-to-analog converter is therefore connected to the input E
1
and the values injected are measured accurately. During the normal operation phase, the digital-to-analog converter included in the feedback loop is connected to the input E
2
of the adder. Because the capacitors C
1
and C
2
are in practice different, the values measured during the calibrat
France Telecom
Meyertons Eric B.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Wamsley Patrick
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