Method for compensating non-linearity of a sigma-delta...

Details Method for compensating non-linearity of a sigma-delta... Method for compensating non-linearity of a sigma-delta...

2011-05-24

2011-05-24

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000, C341S143000

Reissue Patent

active

RE042387

ABSTRACT:
The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A2) with quantization at N levels comprising a digital-to-analog converter (24). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A2) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A2) is operating with quantization at N levels, in producing an instantaneous correction of errors of the analog-to-digital converter (24) using said correction values.

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patent: 0001754 (2000-06-01), None
Sarhang-Nejad and Temes: A High-Resolution Multibit ADC with Digital Correction and Relaxed Amplifier Requirements IEEE Journal of Solid-Stat Circuits, vol. 28, No. 6, Jun. 1993, pp. 648-660.
Search report for PCT/FR 00/01754; Entitled: Method for Compensating Non-Linearity of a Sigma-Delta Analog-To-Digital Converter.

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