Method for combining logic circuit and capacitor

Details Method for combining logic circuit and capacitor Method for combining logic circuit and capacitor

1999-10-22

2001-08-28

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000, C438S720000

Reexamination Certificate

active

06281134

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates about a method for combining logic circuit and capacitor circuit, more particularly for precisely controlling the shape and area of the inter-metal line, increasing capacitor and reducing electrical resistance.
2. Description of the Prior Art
Currently, demand for integrated circuit (I.C.) has rapidly increased due to widespread use of electronic equipment. In particular, the increasing popularity of some electronic equipment such as, for example, many kinds of computers are gradually increasing the demand for the large or very large semiconductor memories in this modern century and next coming twenty-one century. Therefore, the advanced manufacture technology for improvement fabrication of integrated circuit should be urgently need than before.
Normally, the size and performance of the power IC devices depends critically on a specific at a particular breakdown voltage of the output devices. Since the thickness of semiconductor is usually limited by technological constraints, higher breakdown voltages typically require more layers. However, since the device on resistance is proportional to the expitaxial layer resistivity, higher breakdown voltages have to generally be traded off for limited drive current capability.
Thus, there is a conventional method described as referring with
FIG. 1A
, which is the method for combining logical circuit and passive capacitor. Firstly a semiconductor wafer
10
is provided, which concludes a first oxide layer
112
of a first contact
110
upon, of course, there are element structures inside semiconductor wafer
10
. Then, a first metal layer
114
and
116
is deposited respectively on the first contact
110
and around estimated position. The first metal layer
114
is located in logic circuit
12
and another first metal layer
116
is located in capacitor
14
, as an lower electrode of capacitor shown on FIG.
1
B.
Sequentially, as
FIG. 1C
, second oxide
118
is overlapped upon semiconductor wafer
10
and first metal layer
114
and
116
.
FIG. 1D
shows, a second metal layer
120
, as an upper electrode is deposited upon first metal layer
116
through second oxide layer
118
. Then, second contact
124
, third contact
126
and fourth contact
128
are formed by etching third oxide layer
122
which is upon portions of first metal layer
114
and
116
and portions of second metal layer
120
, and inside second metal layer
118
and third oxide layer
122
. Consequentially a tungsten layer is overlapped as a tungsten plug and etched back using the dry etching method or the chemical mechanical polishing (CMP) method, shown as FIG.
1
E.
Finally, aluminium metal layer
130
is deposited and overlapped on second contact
124
, third contact
126
, fourth contact
128
, third oxide layer
122
and semiconductor wafer
10
. Then this aluminium metal layer
130
is etched as a metal via, referring with FIG.
1
F. Then logic circuit
12
and capacitor
14
can be connected through outer line.
From the prior art, the disadvantages of manufacture process for combining logic circuit and capacitor circuit are the following:
1. The size of aluminium metal line is difficult to be controlled very well in the nano-size for the manufacture of semiconductor. It also will reduce the performance and reliability of semiconductor elements.
2. The value of capacitor will be reduced in the semiconductor elements.
3. The resistance of aluminium metal line is not satisfied the requirement of semiconductor elements.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for manufacturing the logic circuit and the capacitor circuit that substantially solving the conventional process problem and producing the purpose semiconductor.
In one embodiment, the method for combining logic circuit and capacitor circuit, normally concludes the following steps. First of all, a semiconductor wafer is provided. Also, the semiconductor wafer owns a first dielectric layer and a first contact formed on the semiconductor wafer. The first metal layer is formed on the first contact and around a estimated area. The first metal layer of the first contact is located on the estimated logical circuit area. The first metal layer is on the estimated capacitor circuit area. The second dielectric layer is formed onto the first metal layer and the first dielectric layer. The second metal layer is formed which is on areas of the metal layer of the estimated areas. The second electric layer abuts on areas of the second dielectric layer. The third dielectric layer is formed on the second metal layer and the second dielectric layer. The fourth dielectric is formed on the third dielectric layer. The fifth dielectric layer is formed on the fourth dielectric layer. Sequentially the fifth dielectric layer and the fourth dielectric layer and the third dielectric layer and the second dielectric layer are all etched. The above steps can form a second contact, which is on portions of the first metal layer of estimated areas. The third contact is located on the second metal layer. The fourth contact is located on the first metal layer of the first contact. The fifth dielectric layer is etched. Here, the second contact and the third contact and the fourth contact inside the fifth dielectric layer is bigger than the second contact and the third contact and the fourth contact inside the third dielectric layer. The barrier layer is formed into the two side walls and bottom, also into the second contact and the third contact and the fourth contact. The inter-metal line is formed into the second contact and the third contact and the fourth contact. The inter-metal line is planarized. Finally, the outer connection line is formed, it can combine the logical circuit and the capacitor circuit.


REFERENCES:
patent: 5689126 (1997-11-01), Takaishi
patent: 5916823 (1999-06-01), Lou et al.
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6037216 (2000-03-01), Liu et al.

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