Method for clock skew cost calculation

Details Method for clock skew cost calculation Method for clock skew cost calculation

1995-10-19

1998-04-14

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

057400679

ABSTRACT:
The present invention provides a method of computing the cost of a proposed clock tree change in the context of a clock skew optimization routine. According to the present invention, a recalculation of the clock skew cost due to a proposed change in the clock tree can be done without having to recompute the effect of the change to all of the sinks of that clock tree. The method stores the effects of past delay changes as unpropagated incremental changes until future changes make it necessary to propagate those changes. Thus, in this method only the parameters of the ancestors of the delayed node need to be recalculated to determine the cost of a proposed change in the clock tree. Not having to recalculate the rest of the tree greatly reduces the computational complexity and time required for the process, allowing the required iterations to be completed in a much shorter time period.

REFERENCES:
patent: 3654615 (1972-04-01), Freitag
patent: 4495559 (1985-01-01), Gelatt, Jr. et al.
patent: 4607339 (1986-08-01), Davis
patent: 4615010 (1986-09-01), Davis et al.
patent: 4931944 (1990-06-01), Richter et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5159682 (1992-10-01), Toyonaga et al.
patent: 5200908 (1993-04-01), Date et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5225991 (1993-07-01), Dougherty
patent: 5235521 (1993-08-01), Johnson et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5308798 (1994-05-01), Brasen et al.
patent: 5333032 (1994-07-01), Matsumoto et al.
patent: 5339253 (1994-08-01), Carrig et al.
patent: 5349536 (1994-09-01), Ashtaputre et al.
patent: 5359535 (1994-10-01), Djaja et al.
patent: 5363313 (1994-11-01), Lee
patent: 5388055 (1995-02-01), Tanizawa et al.
patent: 5402357 (1995-03-01), Schaefer et al.
patent: 5410491 (1995-04-01), Minami
patent: 5416718 (1995-05-01), Yamazaki
patent: 5508937 (1996-04-01), Abato et al.
patent: 5557779 (1996-09-01), Minami
Kudoh, M., et al., LSI Low Power Oriented Layout Method with Net Switching Factors, IBM Technical Disclosure Bulletin, Jun. 1993, vol. 36, No. 06B, pp. 505-507.
Gonsalves, G. J., Technology Mapping Using Simulated Annealing, IBM Technical Disclosure Bulletin, Aug. 1990, vol. 33, No. 3A, p. 308.
Author Unknown, Method to Achieve Equal Capacitance on a Group of Nets During Curcuit Layout and Placement, Research Disclosure, Mar. 1989, No. 299, Kenneth Mason Publications Ltd., England.
Lam, Jimmy, et al., Performance of a New Annealing Schedule, IEEE, 1988 pp. 306-311.
Darema-Rogers, F., et al., Parallel Simulated Annealing Method for Highly Parallel Multiple Computer Processors, IBM Technical Disclosure Bulletin, Dec. 1987, vol. 30, No. 7 pp. 106-107.
Huang, M. D., et al., An Efficient General Cooling Schedule for Simulated Annealing, IEEE,1986, pp. 381-384.
Kirkpatrick, S., et al., Optimization by Simulated Annealing, Science, May 13, 1983, vol. 220, No. 4598, pp. 671-680.

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