Method for clock-pulse selection in a baseband combiner and...

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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C375S350000, C455S134000

Reexamination Certificate

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07035362

ABSTRACT:
Described is a method for the clock-pulse selection in a baseband combiner of a space-diversity receiver. The method provides for driving the clock recovery circuit by means of the main signal, filtered and sampled, or by the diversity signal, filtered and sampled as well, and it is characterized by calculating the average power of the equalized main signal and the average power of the equalized diversity signal; and by driving the clock recovery circuit by means of the signal chosen according to a comparison between the average powers of the signals at the output of the equalizers. Advantageously, the invention provides for a hysteresis on the power comparison and guarantees a soft change with respect to the selection performed at the preceding time of processing.

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patent: 2001/0030991 (2001-10-01), Imai et al.
Floyd M Gardner: “a BPSK/QPSK Timing-Error Detector for Sampled Receivers”, IEEE Transactions on Communications, vol. COM-34, No. 5, May 1986, pp. 423-429.
Gugliemlmi F et al.: “Blind Algorithms for Joint Clock Recovery and Baseband Combining in Digital Radio” European Conference on Radio Relay Systems. Edinburgh, Oct. 11-14, 1994, London, IEE, GB, vol. CONF. 4, Oct. 11, 1993, pp. 279-286.
Patent Abstracts of Japan, vol. 016, No. 432 (E-1262), Sep. 9, 1992 & JP 04 150320 A (NEC Corp.), May 22, 1992.

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