Method for clock generator lock-time reduction during...

Details Method for clock generator lock-time reduction during... Method for clock generator lock-time reduction during...

2005-07-05

2005-07-05

Shingleton, Michael B (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S025000, C331S034000

Reexamination Certificate

active

06914490

ABSTRACT:
A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency. Through this method, frequency change is accomplished without performing a startup process and the time to perform a frequency acquisition process is significantly reduced.

REFERENCES:
patent: 6329882 (2001-12-01), Fayneh et al.
patent: 6763478 (2004-07-01), Bui
patent: 2001/0017572 (2001-08-01), Harpham
Milman, Microelectronics Digital and Analog Circuits and Systems, McGraw-Hill Book Company, 1979 pp 313-315.

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