Method for clearing memory contents and memory array capable of

Details Method for clearing memory contents and memory array capable of Method for clearing memory contents and memory array capable of

1999-09-07

2000-11-07

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365154, 365156, G11C 800

Patent

active

061446114

ABSTRACT:
The present invention provides a means for clearing or wiping the contents of a RAM array without the need for overly large transistors and without experiencing current spikes by using a progressive row-by-row clearing operation. In reference to FIGS. 4 and 5, progressive row clearing is achieved by the addition of a transistor (72) in series with the row RAMWIPE transistor (e.g. transistor 69) in each row. Transistor 72 is gated by a signal PRS (Previous Row Select). PRS for a given row will be asserted or enabled only when the previous row in the array is also selected or enabled. A given row is only selected for clearing in a wipe operation when both a RAMWIPE signal and a PRS (previous row select) signal are asserted. The next row, therefore, is not cleared until the previous row is cleared.

REFERENCES:
patent: 4412309 (1983-10-01), Kuo
patent: 5394373 (1995-02-01), Kawamoto
patent: 5907505 (1999-05-01), Tomita
patent: 5949735 (1999-09-01), Jeong

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