Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Utility Patent
1999-03-25
2001-01-02
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C134S001200, C134S001300, C204S192370, C216S039000, C216S057000, C438S675000, C438S706000, C438S722000, C438S723000
Utility Patent
active
06169036
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of semiconductor processing, and, more particularly, to a method for cleaning via openings.
BACKGROUND OF THE INVENTION
Integrated circuits are used in many electronic devices, such as cellular telephones, personal computers, radios, televisions, etc. A typical integrated circuit includes a plurality of active semiconductor device regions formed in a substrate of semiconductor material. Two or more metal interconnect layers are used to connect various portions of the integrated circuit. Adjacent metal interconnect layers are separated by one or more dielectric or insulating layers. Typically an electrical connection or contact is established between adjacent vertical portions of two different metal interconnect layers.
Such a vertical electrical connection is conventionally made by forming a via opening in a dielectric layer thereby exposing a portion of the underlying metal interconnect layer. This via opening is typically cleaned and filled with conductive material to form the vertically extending conductor or contact. One or more barrier metal layers may be formed to first line the via opening before filling the rest of the opening.
As discussed, for example, in U.S. Pat. No. 5,451,543 to Woo et al., as semiconductor device dimensions continue to be reduced, one limiting factor remains the area required for device interconnections. The use of multilevel metallizations partially address this difficultly. However, the area available for via openings is also being reduced and the electrical resistance posed by smaller resulting contacts creates difficulties in further reducing dimensions. During a typical via etching process, the etching tends to create metal oxide, such as, for example, aluminum oxide, which becomes deposited on the sidewall of the via opening. This causes a tapering of the via opening such that the bottom portion is much smaller in area than the top portion. An organic solvent has been used to remove the residue of aluminum oxide from the via sidewalls. Unfortunately, the use of the solvent also attacks the exposed aluminum and may result in poor coverage of a subsequent barrier layer.
U.S. Pat. No. 5,661,083 to Chen et al. discloses an approach to removing such sidewall and bottom residue in a via opening wherein a portion of an etch stop layer is removed using a reactive ion etch and downstream microwave ash system under conditions effective to create a substantially water-soluble polymer residue within the via. The water-soluble polymer is then removed to expose the underlying metal layer.
Despite advances in creating via openings with smaller dimensions and more consistent dimensions from top to bottom, there still exists a need to improve techniques as feature sizes continue to be reduced. Problems continue to exist with redeposition of metal oxides on the via sidewalls. The copper oxide layer should be effectively removed from the bottom of the via opening to form a low resistance electrical contact in the via opening.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the invention to provide a method for cleaning via openings that will provide for a lower contact resistance while permitting a high density of interconnections as semiconductor feature sizes continue to be decreased.
This and other objects, features and advantages in accordance with the present invention are provided by a method for cleaning a via opening of an integrated circuit, the via opening including sidewalls and an exposed metal portion at a bottom thereof. By efficiently cleaning the via opening the contact resistance is lowered. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. In some embodiments, the step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere.
In one embodiment of the invention, the exposed metal portion comprises a metal compound, such as a metal oxide, oxi-nitride, sulfide or mixtures thereof. Accordingly, the step of sputter cleaning removes at least a portion of the metal compound, and the step of exposing preferably comprises reducing at least a portion of the metal compound. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.
In accordance with another advantageous feature of the invention, the use of both sputter cleaning and exposure to the reducing atmosphere provides for upper corners of the via opening to have a predetermined amount of bevel. For example, if sputter cleaning alone were used, the upper edges of the sidewalls of the via opening would likely be beveled too severely, and the ability to maintain a high interconnect density would be sacrificed. According to the present invention, the combination of both sputter cleaning and exposure to the reducing atmosphere removes the residue from the sidewalls of the via opening and removes the metal compound from the exposed metal layer, while maintaining a desired degree of beveling of the upper corners of the via opening.
The step of sputter cleaning preferably comprises performing a plasma assisted sputtering, such as using argon, for example. The step of exposing may comprise exposing the via opening to a reducing ion
eutral treatment, that is, to treatments other than oxidation. For example, the reactive ion treatment may include exposing the via opening to a hydrogen containing plasma. Alternatively, the step of exposing the via opening to a reducing atmosphere may comprise exposing the via opening to an ammonia gas dissociated by an elevated temperature or a plasma. Another advantageous feature of the invention is that the sputter cleaning and reducing steps may be performed in one processing chamber.
Another method aspect of the invention is for making an integrated circuit incorporating the method of cleaning via openings discussed above. The integrated circuit thus produced enjoys low contact resistance, and because the beveling of the upper corners of the via openings can be accurately controlled, the pitch or density of interconnects can be relatively high.
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Bhowmik Siddhartha
Buckfeller Joseph William
Clabough G. Craig
Merchant Sailesh Mansinh
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Lucent Technologies - Inc.
Powell William
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