Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-04-26
2002-03-12
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S725000, C438S704000, C438S974000, C438S963000
Reexamination Certificate
active
06355576
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor processing and, more particularly to methods for processing wafers in preparation for wire bonding.
In the manufacture of integrated circuits, a conductive metal pad, such as aluminum copper alloy (ALCu) pad, is typically used allow the electrical connection between active elements of the integrated circuit the external world. More specifically, gold wires or bumps are typically connected to bonding pads formed of this uppermost layer of metal.
In the fabrication of integrated circuits, after the uppermost metal layer is formed, an insulating or dielectric “blanket” layer is deposited over the metal layer. Thereafter, to enable external electrical conuections to the chip, vias are etched through the blanket layer to expose portions of the underlying metal layer. These exposed regions of the metal layer are called “bonding pads.” A clean, residue-free bonding pad surface is desired for optimal bonding of the bond wires to the bonding pads. Otherwise, residues on the bonding pad surface can degrade the reliability of the wire bonds. However, conventional processes for forming bonding pads do not tend to produce clean, residue-free bonding pads.
A conventional process for forming a bonding pad is shown in
FIGS. 1-4
.
FIG. 1
shows a typical bonding pad region
10
of an integrated circuit. The layers that compose the region begin with the uppermost metal layer
12
, typically AL. Above the metal layer, an optional titanium nitride (TiN) or titanium tungsten (TiW) alloy layer
14
is provided for the bonding pad surface. Above the alloy layer, are dialectic layers composed of silicon dioxide
16
and silicon nitride
18
. A resist mask
20
is then deposited above the dielectric layers to facilitate the pad etch process.
FIG. 2
shows the bonding pad region
10
after a typical pad etch. Using a dielectric etcher and gases
22
such as CHF
3
, CF
4
, or SF
6
, the nitride
18
, oxide
16
, and alloy
18
layers are all etched. This etch exposes the uppermost metal layer
12
, thus creating a bonding pad area
24
. However, the etch process leaves fluorine residues
26
on the pad surface
24
, and metallic polymers
28
on the sidewalls. The fluorine residues
26
bond with the underlying AlCu, and cannot be easily removed.
After the pad etch, an asher is typically used to ash the resist
20
.
FIG. 3
shows the bonding pad region after an ash treatment. The resist
20
has been removed exposing the upper surface of the nitride
18
dielectric layer. After the resist is ashed, a wet cleaning is performed on the bonding pad to remove residue. The wet cleaning, however, cannot remove all the etch process residue
26
, since much of the fluorine residue has bonded to the bonding pad. In addition, the metallic polymers
28
are not soluble in the solvents normally used, thus they remain on the sidewall after wet cleaning.
If the wafer is allowed to sit for any amount of time, or if it collects any kind of moisture, the fluorine residue
26
in the bond pad
24
will migrate to the surface and form a fluorine crystal
30
. This crystal prevents a reliable bond with the bond pad surface. Thus, a bond wire
32
may break away from the bond pad
24
after bonding, or form a high resistance connection to the bonding pad.
Bonding pad failure reduces the yield of functional integrated circuits, and thus increases their cost. Further, poor bonding pad connections reduce the reliability of the integrated circuits.
In view of the above, it is apparent that an improved process for creating a clean, reliable bonding pad surfaces is required. Such a process should not leave substantial imbedded residue in the bonding pad surface. In addition, it should meet the demands of high volume manufacturing by not requiring undue time to execute, or additional machinery.
SUMMARY OF THE INVENTION
The present invention meets the aforementioned requirements by providing a process that treats a bond pad surface with a CF
4
and water vapor combination. This volatizes the fluorine from the bond pad surface and softens the metallic polymers adhering to the sidewalls. In the process, hydrogen from the water vapor breaks up and couples to the fluorine creating HF, which is volatile in a plasma. As a result, the fluorine is removed from the bond pad surface before it has a chance to crystallize, resulting in a clean bond pad surface. The invention produces clean, reliable bonding pad surfaces resulting in drastically reduced bond wire failure. Furthermore, it does not require undue time to perform and requires no additional machinery.
One aspect of the present invention teaches a method for treating a bond pad surface with a CF
4
and water vapor combination. During the process, the CF
4
and water vapor are ionized. The ionization causes the hydrogen from the ionized water to combine with the fluorine residue on the bonding pad surface, creating a volatile HF vapor. In addition, fluorine from the ionized CF
4
exchanges with metal from the metallic polymer residue causing the polymers to soften. The process then includes ashing the resist layer, followed by stripping the wafer in a liquid solvent to remove contaminants including the metallic polymers. This process prevents fluorine crystallization and provides a clean bond pad surface.
Another aspect of the present invention teaches a system for cleaning integrated circuit bonding pads including a plasma asher, an organic stripper, and back end processors for completing the chips. The asher must be capable of treating an integrated circuit with a CF
4
and water vapor combination to volatize the fluorine and soften the metallic polymers.
These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following descriptions and study of the various figures of the drawings.
REFERENCES:
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patent: 5630904 (1997-05-01), Aoyama et al.
patent: 5660681 (1997-08-01), Fukuda et al.
patent: 5705419 (1998-01-01), Perry et al.
patent: 5770523 (1998-06-01), Hung et al.
patent: 5895245 (1999-04-01), Harvey et al.
patent: 5925577 (1999-07-01), Solis
patent: 5930664 (1999-07-01), Hsu et al.
patent: 5970376 (1999-10-01), Chen
patent: 6043165 (2000-03-01), Park et al.
K.H. Ernst, D. Grman, R. Hauert. E. Hollander; Flourine-induced Corrosion of Aluminum Microchip Bond Pads; an XPS and Analysis, Surface and Interface Analysis, vol. 21, 691-696 (1994).
Galloway Judy
Haley Mark
Parks Delbert
Oppenheimer Wolff & Donnelly LLP
Richards N. Drew
VLSI Technology Inc.
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