Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-08-16
2011-08-16
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S102000, C716S103000, C716S105000, C716S106000, C716S108000, C716S111000, C716S117000, C716S138000
Reexamination Certificate
active
08001501
ABSTRACT:
A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.
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Dorsch Rainer
Junginger Marta
Salz Philipp
Wagner Andreas
Zilles Gerhard
International Business Machines - Corporation
Rossoshek Helen
Schmeiser Olsen & Watts
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