Method for chemical/mechanical planarization of a...

Details Method for chemical/mechanical planarization of a... Method for chemical/mechanical planarization of a...

1999-10-08

2003-07-22

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S626000, C438S633000, C438S699000

Reexamination Certificate

active

06596639

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to semiconductor manufacturing and, more specifically, to a method involving applying a sacrificial material to a substantially planar condition prior to planarizing a semiconductor wafer having an interlayer dielectric over dissimilar metal pattern density areas.
BACKGROUND OF THE INVENTION
Dielectric and metal layers used in chip fabrication today must be made extremely flat and of precise thickness in order to photolithographically pattern the sub-micron sized features that comprise a semiconductor device. During chemical/mechanical planarization (CMP), the combination of chemical etching and mechanical abrasion produces the required flat, precise surface for subsequent depositions.
Commonly, the functional complexity of the circuits with shrinking dimensions is limited by the characteristics of the metallic conductors (commonly referred to as interconnects) that provide the electrical connections between the circuit elements. Key characteristics considered when employing such interconnects are the minimum width and separation of the conductor features as well as the total number of interconnect levels that are required. The non-planarity of the top surface of an integrated circuit is determined by the cumulative non-planarity of all the underlying levels. Therefore, as the number of underlying interconnect levels is increased, the planarization precision at each level becomes more important as errors are cumulative to the uppermost level. For a more thorough discussion of planarization and the effects of non-planarity on photolithography, see S. Wolf's,
Silicon Processing for the VLSI Era, Vol.
2, which is incorporated herein by reference.
CMP preferentially removes the high portions of whatever layer is being planarized. In many instances, the layer is an interlayer dielectric (ILD) that occurs in areas directly above underlying interconnect topography. During deposition, the ILD follows the general contours of the previous layer, such that relatively complex interconnect areas have resultant large contiguous dielectric deposition thereon. That is, during deposition the dielectric “mushrooms” around each feature as the feature acts like a stem of a mushroom. Referring initially to
FIGS. 1A-1B
, illustrated are sectional views of a conventional planarization process.
FIG. 1A
illustrates a sectional view of three different areas of interconnect pattern density
110
,
120
,
130
with a dielectric layer
140
deposited thereon. Pattern density is defined, for this discussion, as the normalized percentage of the total surface area of a substrate that is covered with interconnects. For example, pattern density may be expressed as the percentage of metal interconnect area per surface area. Thus, closely spaced interconnects will have a higher pattern density. With a single interconnect
111
, the dielectric
140
forms a mushroom
112
about the single interconnect
111
that is essentially equal on each side
111
a
,
111
b
of the interconnect
111
. When dual interconnects
121
,
122
are sufficiently close, a mushroom
123
extends to either side of the outermost interconnect sides
126
,
127
. In the case of a plurality of conventional interconnect structures (designated as
131
a-
131
n
), the dielectric layer
140
forms such that the surface
133
over the interconnects
131
a-
131
n
is essentially planar, while the mushroom
134
forms beyond outer edges
136
and
137
of the outermost interconnects
131
a
,
131
n
. As can be seen, between areas
110
,
120
, and
130
, valleys
150
occur in the dielectric
140
where interconnects do not exist.
FIG. 1B
illustrates the results of a CMP process performed on the interconnect densities of FIG.
1
A. During the CMP process, the dielectric removal rate is slower for regions with a high density
130
of underlying interconnect structures because a large fraction of the wafer surface contacts the polishing pad in these regions. One who is skilled in the art is familiar with conventional CMP processes. Conversely, areas of low pattern interconnect density
110
,
120
encounter significantly faster removal of material during CMP. Consequently, the height of the dielectric layer
140
may vary dramatically across the chip depending on the underlying metal pattern density. While the surface
141
of the dielectric layer
140
is locally planar, the pattern density variation in the underlying interconnect structures
110
,
120
,
130
creates an unacceptable amount of non-planarity in the dielectric surface
141
as indicated by the variation in the dielectric layer thicknesses
115
,
125
,
135
in different areas of the die. Following the CMP process, thicknesses
115
,
125
,
135
will vary, such that: thickness
115
is less than thickness
125
, is less than thickness
135
. Therefore, the desired planarity is jeopardized.
One approach that has been taken to compensate for this problem is termed metal topography reduction (MTR), which is discussed in U.S. patent application Ser. No. 09/298,792 filed on Apr. 23, 1999 entitled “Method of Planarizing a Surface of an Integrated Circuit” which is incorporated herein by reference. This involves forming a photoresist material over selected recessed areas of a die such as the valleys
150
of
FIG. 1A
, etching the photoresist, and then partially etching into protruding areas
112
,
123
,
133
to roughly level the die surface. The semiconductor die are then conventionally planarized. Of course, this introduces an additional photolithographic step and a plasma etch of the dielectric to reduce the area of the dielectric in those areas with a high area density of metal. This somewhat reduces the effects of the higher and lower pattern densities. While some success has been achieved with metal topography reduction, the additional photolithographic and etching steps are both expensive and time consuming.
Accordingly, what is needed in the art is an inexpensive method of preparing a semiconductor wafer for chemical/mechanical planarization of the interlayer dielectric.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing an integrated circuit including planarizing an irregular semiconductor wafer surface. In one embodiment, the method comprises forming an interlayer dielectric over a first level having an irregular topography, depositing a sacrificial material over the dielectric layer, and then planarizing the semiconductor wafer surface to a planar surface. More specifically, the dielectric layer forms such that it substantially conforms to the irregular topography of the first level. The sacrificial material is formed to a substantially planar surface over the dielectric layer. Thus, the sacrificial material provides a substantially uniform chemical/mechanical planarization (CMP) process removal rate across the semiconductor wafer surface. In the ensuing step, planarizing the semiconductor wafer surface to a planar surface removes the sacrificial material and a portion-of the dielectric layer with the CMP process.
Thus, in a-broad aspect, a sacrificial material is deposited upon an interlayer dielectric that has conformed to an underlying, irregular topography. The sacrificial material forms a substantially planar surface over the irregular topography, and it has a CMP process removal rate substantially equal to the removal rate of the dielectric layer. For this discussion, a substantially planar surface is a surface where the difference between the highest and lowest points is no greater than about 15 percent to 20 percent of the thickness as measured from a datum plane. Therefore, in the immediately ensuing step of planarizing, the dielectric layer and sacrificial material are removed at substantially the same rate, resulting in a planar surface. A planar surface, for this discussion, is a surface where the difference between the highest and lowest points is less than about 10 percent of the

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