Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-07-19
2011-07-19
Memula, Suresh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S111000
Reexamination Certificate
active
07984401
ABSTRACT:
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
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Barandiaran Jose
Lehavot Amir
Scherer Axel Siegfried
Singh Vinaya Kumar
Zachariah Joezac John
Cadence Design Systems Inc.
Memula Suresh
Sawyer Law Group P.C.
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