Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-07-03
1998-11-17
Le, Vu A.
Static information storage and retrieval
Floating gate
Particular biasing
36518519, 36518526, G11C 700
Patent
active
058386173
ABSTRACT:
A process for introducing negative charge onto the floating gate of an EPROM or EEPROM device is disclosed. The process uses CHISEL conditions to introduce charge onto the floating gate. The threshold voltage of the device is controlled by selecting a control gate voltage during programming that is less than 10 volts and that will provide a device with the desired threshold voltage. The device is then programmed using the selected control gate voltage and a negative substrate bias.
REFERENCES:
patent: 5042009 (1991-08-01), Kazerounian et al.
patent: 5222040 (1993-06-01), Challa
patent: 5278439 (1994-01-01), Ma et al.
patent: 5327378 (1994-07-01), Kazerounian
patent: 5349220 (1994-09-01), Hong
patent: 5357476 (1994-10-01), Kuo et al.
patent: 5364806 (1994-11-01), Ma
patent: 5381051 (1995-01-01), Morton
patent: 5390068 (1995-02-01), Schultz et al.
patent: 5394365 (1995-02-01), Tsukikawa
patent: 5412603 (1995-05-01), Schreck et al.
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5491657 (1996-02-01), Haddad
patent: 5511021 (1996-04-01), Bergemont et al.
patent: 5546340 (1996-08-01), Hu et al.
"Process and Device Technologies for 16Mbit EPROMs wth Large-Th Large-Tilt-Angle Implantaed P-Pocket Cell", by Ohshima, Y. et al., IEDM Tech. Dig., pp. 95-98 (1990).
"Fast Programmable 256K Read Only Memory with On-Chip Test Circuits", by Atsumi, S. et al., IEEE Solid-State Circuits, vol. 2C-20, No. 1, pp. 422-427 (Feb. 1985).
"A Temperature and Process-Tolerant 64K EEPROM", by Bill, C. S. et al., IEE J. Solid-State Circuits, vol. SC-20, No. 5 pp. 979-985 (Oct. 1985).
"A 5 Volt High Density Poly-Poly Erase Flash Eprom Cell", by Kazerounia, R. et al., IEDM Tech. Dig., pp. 436-439 (1988).
"A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory", by Onoda, H., et al., IEDM, 92-599, pp. 24.3.1-24.3.4 (Apr. 1992).
"E-PROM's Integrity Starts With its Cell Structure", by Woods, M. H., Electronics Magazine, pp. 59-68 (Aug. 1980).
"Endurance Brightens the Future of Flash", by Robinson, K., Electronic Component News, pp. 167-169 (Nov. 1988).
"Nonvolatile Semiconductor Memories", Edited by Hu, C. IEEE Electron Devices Society, pp. 1-9.
"EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing", by Bude, J. D., et al., IEDM, pp. 3.7.1-3.7.3 (95-989).
"A Fullyl Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory", by Frohman-Bentchkowsky, D., IEE J. Solid-State Circuits, vol. SC-6, No. 5, pp. 301-306 (Oct. 1971).
Bude Jeffrey Devin
Pinto Mark Richard
Botos Richard J.
Le Vu A.
Lucent Technologies - Inc.
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