Method for capturing ASIC I/O pin data for tester compatibility

Details Method for capturing ASIC I/O pin data for tester compatibility Method for capturing ASIC I/O pin data for tester compatibility

1996-12-23

1999-11-30

Teska, Kevin J.

39550034, 39550036, G06F 1320, G06F 9455

Patent

active

059957409

ABSTRACT:
The present invention includes a modeling and testbench creation methodology which will allow a simulator to provide information regarding the state and direction of a bi-directional pad or pin. The present invention provides ATE tools all of the required data used to accurately and efficiently check for tester compatibility for which test patterns are extracted. In particular, the present invention includes a method of modeling a bi-directional I/O pad that includes the steps of providing a first signal in a first model; providing a second signal in a second model; and determining contention and direction of a resolved signal that is generated in response to at least one of the input and output signals. The first signal is a preferred output signal that is contained within an ASIC (first) model. The second signal is a preferred input signal that is contained within a testbench (second) model.

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