Method for calibrating variable delay circuit and a variable del

Data processing: measuring – calibrating – or testing – Calibration or correction system

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

702176, 324130, 714724, 73 5, G01D 1800

Patent

active

061637599

ABSTRACT:
In a variable delay circuit calibrating method in which the state of connection of M delay stages connected in cascade through multiplexers and weighted differently is controlled by a control signal value to generate a calibrated amount of delay corresponding to a nominal amount of delay D.sub.s which varies in a predetermined minimum nominal delay step d.sub.s, the method comprises the steps of: dividing an amount of delay D.sub.i measured for each given control signal value CC.sub.i by the minimum nominal delay step d.sub.s of a variable delay circuit; calculating first and second errors, R.sub.k =D.sub.i -d.sub.s k and R.sub.k+1 =d.sub.s -R.sub.k, between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay D.sub.sk and D.sub.sk+1 ; making a check to determine if the first error R.sub.k is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k; if so, writing the first error R.sub.k and the corresponding control signal value CC.sub.i over the existing values in the column of the k-th row of the calibration table; making a check to determine if the second error R.sub.k+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1; and, if so, writing the second error R.sub.k+1 and the corresponding control signal value CC.sub.i over the existing values in the column of the (k+1)-th row of the calibration table. By repeatedly executing these steps for i=0 to i=2.sup.M -1, control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS.

REFERENCES:
patent: 4263803 (1981-04-01), Burkhardt
patent: 5457719 (1995-10-01), Guo et al.
patent: 5811655 (1998-09-01), Hashimoto et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for calibrating variable delay circuit and a variable del does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for calibrating variable delay circuit and a variable del, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for calibrating variable delay circuit and a variable del will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-277566

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.