Method for calculating tolerable value for fluctuation in...

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system

Reexamination Certificate

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C327S065000, C716S030000

Reexamination Certificate

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07630845

ABSTRACT:
A method for calculating a tolerable value for simultaneous switching noise in an input/output circuit having a differential input supplied with a power supply voltage. The method includes providing an input/output circuit having a differential input unit with a pulse signal of a predetermined duty ratio, setting a tolerable range for the duty ratio of the output signal of the input/output circuit with respect to the pulse signal, changing the power supply voltage supplied to the differential input unit of the input/output circuit, measuring the duty ratio of the output signal corresponding to the voltage change, comparing the measured duty ratio with the tolerable range, and calculating a tolerable value for the simultaneous switching noise.

REFERENCES:
patent: 4590433 (1986-05-01), Kusakabe
patent: 4594677 (1986-06-01), Barlow
patent: 5477460 (1995-12-01), Vakirtzis et al.
patent: 6041169 (2000-03-01), Brennan
patent: 6564355 (2003-05-01), Smith et al.
patent: 7139691 (2006-11-01), Duong
patent: 2006/0270113 (2006-11-01), Dan et al.
patent: 2005-038400 (2005-02-01), None
R. Senthinathan et al.; “Simultaneous Switching Noise of CMOS Devices and Systems”; Kluwer Academic Publishers, 1994; (pp. 23-28).

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