Method for calculating a result of a division with a...

Details Method for calculating a result of a division with a... Method for calculating a result of a division with a...

2011-01-18

2011-01-18

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07873687

ABSTRACT:
The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, wherein while loading the fraction of the dividend through the divisor register into the partial remainder register of the divide processor a calculated shifting is applied for alignment by using the multiplier associated to the subtractor.

REFERENCES:
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patent: 2006/0184601 (2006-08-01), Trong et al.
patent: 2008/0275931 (2008-11-01), Schmookler
G. Gerwig et al. “The IBM eServer z990 Floating-Point Unit”, IBM Journal of Research and Development, vol. 48, No. 3/4, May /Jul. 2004. pp. 311-322.
IBM z/Architecture Principles of Operation, SA22-7832-03, 4th Edition, May 2004.

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