Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1994-11-28
1996-10-15
Nelms, David C.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36523003, 365233, 365154, G11C 800
Patent
active
055661270
ABSTRACT:
A static random access memory (SRAM) that is configurable for different word widths and memory sizes, and a method for forming the physical layout with blocks of a SRAM are described. In the physical layout of the SRAM, a central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a data bus interface. Memory block macros (35) are formed that include a block of memory, precharge circuits, read/write multiplexers, and sense amplifiers. Memory block macros (35) are symmetrically located around the central block structure (54), and may also include a block deselect circuit (39) and rox/block decoders (38) if multiple memory blocks are used. A deselection process may be used in which the SRAM selects a bit or word by deselection. All memory blocks and memory rows are initially selected with the only a single block and row remaining selected after the deselection process. Block deselect circuits (39) deselect memory blocks (89). Row deselect circuits (21) deselect row drivers (22) from enabling memory rows of memory blocks (89). A delayed clock buffer (29) provides a delayed clock signal for preventing row drivers (22) from enabling a memory row during the deselect process.
REFERENCES:
patent: 5124951 (1992-06-01), Slemmer et al.
patent: 5128897 (1992-07-01), McClure
patent: 5225240 (1993-10-01), Wong
patent: 5301144 (1994-04-01), Kohno
Hoang Huan
Hoshizaki Gary W.
Motorola Inc.
Nelms David C.
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