Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With decomposition of a precursor
Reexamination Certificate
1997-11-20
2001-05-08
Wu, David W. (Department: 1713)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
With decomposition of a precursor
C117S935000, C117S939000, C216S002000
Reexamination Certificate
active
06228166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device fabrication techniques using ULSI (ultra-large-scale integration) technology, and more specifically to a method of effectively lowering boron (B) concentration at an interface between an epitaxially grown film and the Si substrate surface. Such a film may be a Si or Si
1-x
Ge
x
film selectively deposited in an UHV-CVD (ultrahigh vacuum/chemical vapor deposition) apparatus using a source gas(es) such as SiH
4
, Si
2
H
6
, GeH
4
, etc.
2. Description of the Related Art
It is known in the art that the selective epitaxial growth of Si or Si
1-x
Ge
x
on a silicon wafer surface, using an UHV-CVD apparatus with a source gas(es) such as SiH
4
, Si
2
H
6
, or GeH
4
, has found an extensive application in forming about 0.1 &mgr;m level of channel epitaxial construction in a miniaturized MOS (metal-oxide semiconductor) transistors, next generation's high-speed bipolar transistors, etc.
Before turning to the present invention, it is deemed advantageous to describe, with reference to FIGS.
1
(A)-
1
(C),
2
, and
3
, conventional techniques relating to the present invention. Throughout the instant disclosure, term “substrate” is interchangeably used with “wafer”. Although a high-speed bipolar transistor is referred to in this specification, it should be noted that the present invention is in no way limited thereto.
FIGS.
1
(A)-
1
(C) are schematic cross-sectional views depicting the fabrication of a high-speed NPN bipolar transistor. In brief, a substrate wherein a collector portion has been formed as shown in FIG.
1
(A), is transferred to an UHV-CVD apparatus such as that is schematically shown in FIG.
2
. In the UHV-CVD apparatus, a Si or Si
1-x
Ge
x
epitaxial base portion is grown on the substrate as illustrated in FIG.
1
(B). Following this, the wafer (or substrate) is removed from the UHV-CVD apparatus and an emitter portion is formed on the substrate in the manner shown in FIG.
1
(C).
The present invention is directed to effective reduction of boron contamination (or concentration) at an interface between an epitaxially grown film and the Si substrate surface. To this end, each wafer is pretreated before being loaded into the CVD apparatus, and/or a growth chamber of the CVD apparatus is cleaned prior to each CVD process. Thus, it will be understood that the formation of the emitter portion shown in FIG.
1
(C) is not relevant to the present invention.
Referring to FIG.
1
(A), an N
+
layer
10
is grown on an P
+
<100>-oriented Si substrate
12
with resistivity ranging from 10 to 20 &OHgr;cm (for example). Following this, an N
−
epi-layer
14
, which functions as a collector, is deposited on the N
+
layer
10
. Further, as illustrated in FIG.
1
(A), a SiO
2
layer
16
, a P
+
poly-Si layer
18
, and another SiO
2
layer
20
are successively formed using conventional lithography and etching techniques.
The substrate, which has undergone the above processes, is transferred to the UHV-CVD apparatus wherein the Si or Si
1-x
Ge
x
epitaxial base (denoted by numeral
22
) is selectively grown on the N
−
epi-layer
14
. In this case, inner portions of the poly-Si layer
18
grow downwardly as schematically shown in FIG.
1
(B). Subsequently, the substrate shown in FIG.
1
(B) is unloaded from the UHV-CVD apparatus, after which a SiO
2
layer
24
and an N
+
poly-Si emitter layer
26
are formed, as shown in FIG.
1
(C), using conventional techniques. The processes for forming the structure shown in FIGS.
1
(A)-
1
(C) are well known and not directly concerned with the present invention, and thus further description thereof will be omitted for brevity.
FIG. 2
is a diagram schematically showing one example of an UHV-CVD apparatus (denoted by numeral
30
), which comprises a robotic transfer section
32
, two load-lock chambers
34
a
and
34
b,
another robotic transfer section
36
, and two growth chambers
38
a
and
38
b.
The UHV-CVD apparatus
30
per se is well known in the art. Other sections such as turbo pumps, which are irrelevant to the present invention, are not shown in
FIG. 2
for the sake of simplifying the disclosure.
FIG. 2
will also be referred to in the preferred embodiments of the present invention.
The robotic transfer section
32
comprises a clean bench
40
and two substrate transfer robots
42
a
and
42
b,
while the robotic transfer section
36
includes a similar substrate transfer robot
44
.
Each of the substrates or wafers, which has been processed as shown in FIG.
1
(A), is cleaned and then disposed in a substrate carry box
46
a
which is, in this case, positioned in a place other than on the clean bench
40
. This box
46
a
is then transported to the clean bench
40
, as illustrated in FIG.
2
. The precleaned wafers contained in the box
46
s
are loaded on a one-by-one basis, using the robot
42
a,
into the load-lock chamber
34
a.
After all the wafers in the box
46
a
are loaded into the load-lock chamber
34
a,
the chamber
34
a
is pumped down to a predetermined pressure. Once the predetermined pressure is reached, the first wafer in the load-lock chamber
34
a
is introduced, by way of the robot
44
, into the growth chamber
38
a
which is dedicated to non-doping epitaxial growth.
After the epitaxial growth is completed in the chamber
38
a,
the wafer is conveyed to another growth chamber
38
b
which is dedicated to p-type (viz., B) doping epitaxial growth. The reason why the two growth chambers
38
a
and
38
b
are used will be described later. When the film deposition on the wafer at the chamber
38
b
is finished, the wafer is transferred to the load-lock chamber
34
b.
These processes are repeated with each of the wafers stored in the load-lock chamber
34
a.
When all the wafers in the load-lock chamber
34
a
are processed and loaded into the other load-lock chamber
34
b,
they are placed into another substrate carry box
46
b
by the robot
42
b.
The wafers in the box
46
b
are then transported to the next wafer process station, wherein subsequent wafer treatments, such as referred to with respect to FIG.
1
(C), are implemented.
FIG. 3
is a flow chart depicting the steps that characterize the conventional processes which include cleaning and CVD processes. In more specific terms, the Si wafers, on which layers or films shown in FIG.
1
(A) are formed, are precleaned and then transferred to the UHV-CVD apparatus
30
shown in FIG.
2
.
Referring to
FIG. 3
, at step
50
, each Si wafer undergoes a dilute HF (hydrofluoric acid) dip in order to remove native oxide formed on the wafer, after which the chemicals used in step
50
are removed by water washing (step
52
). Immediately thereafter, at step
54
, the wafer is subjected to a well known RCA cleaning process using a cleaning solution, NH
4
OH (ammonia)-H
2
O
2
(hydrogen peroxide)-H
2
O (pure water), thereby removing particles and organic contaminations on the wafer. The cleaning with the aforesaid solution is called “standard cleaning 1 (SC-1)), at NH
4
OH—H
2
O
2
—H
2
O (=1:1.5) (for example) at 60 to 80° C. for 3 to 10 minutes. Following this, at step
56
, the reagents used in step
54
are washed away using pure water, and the wafer is then dried using a spin dryer (step
58
). The above mentioned wafer cleaning is carried out with each of a predetermined number of the wafers. Subsequently, the precleaned Si wafers are accommodated in the box
46
a
(
FIG. 2
) and transported to the clean bench
40
of the UHV-CVD apparatus
30
(FIG.
2
).
The Si wafers in the wafer carry box
46
a
are then successively loaded into the load-lock chamber
34
a
(step
60
). At step
62
, a first wafer in the load-lock chamber
34
a
is loaded into the growth chamber
38
a
by way of the wafer transfer robot
44
. When the first wafer is placed in the growth chamber
38
a,
the chamber is pumped down to a pressure of 10
−9
to 10
−10
torr. At step
64
, the wafer is subjected to a h
Aoyama Tohru
Suzuki Tatsuya
Chol Ling-Siu
Hutchins, Wheeler & Dittmar
NEC Corporation
Wu David W.
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