Metal fusion bonding – Process – With measuring – testing – indicating – inspecting – or...
Reexamination Certificate
1998-11-23
2001-02-27
Ryan, Patrick (Department: 1722)
Metal fusion bonding
Process
With measuring, testing, indicating, inspecting, or...
C228S009000, C228S044700, C228S104000, C228S105000
Reexamination Certificate
active
06193132
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor bonding method for bonding a semiconductor chip such as an IC to a substrate, in a face-down manner, and more specifically to a bonding method capable of detecting an error in terms of position, between an electrode of a semiconductor chip and a wiring line provided on a substrate, after a face-down bonding, by inspecting it from outside, and a device therefor.
As one of the methods for directly mounting and bonding a semiconductor chip such as an IC to a mount substrate such as a print wiring substrate, there is a method in which a surface in which the electrode (bump electrode) of a semiconductor chip is formed is made to face a substrate, and the electrode is directly bonded to the wiring pattern of the substrate. This method is generally called “face-down bonding” since the bonding operation is carried out while holding the surface of the semiconductor chip on which the electrode is formed facing downwards.
In the face-down bonding as above, the joint portion between the electrode and the circuit pattern is covered by the semiconductor chip, and therefore it is difficult to confirm if the bonding has been accurately carried out.
In order to detect whether or not bonding has been accurately carried out, that is, to inspect the accuracy of bonding, the method in which the status of the joint portion between the electrode and circuit pattern is physically observed so as to judge if the bonding is good or no good, is generally employed.
More specifically, there is a method in which a semiconductor device which has been subjected to the face-down bonding is sampled at a certain period, and the semiconductor chip is stripped off or cut from the substrate so as to inspect the joint portion of the electrode, and a method in which the joint portion between the electrode and the circuit pattern is examined from a rear side of the substrate transparently.
The method which involves stripping or cutting the semiconductor chip requires the transfer of a sampled semiconductor chip to a separate device, where the stripping and cutting is carried out, the entire system thereby becoming large in size. Further, the inspection cannot be conducted at real time during the bonding operation.
Further, with the transparent inspection method, it is not possible to obtain a clear image of the joint portion, and therefore an accurate inspection cannot be conducted. More specifically, for example, a ceramic substrate or glass substrate is used as the substrate, and particularly, in the case of the ceramic substrate, the amount of light transmission is very small. As a result, it is very difficult to confirm even the outline of a semiconductor chip, not to mention the joint portion between the electrode and circuit pattern.
Further, in the case where a semiconductor chip is face-down bonded to a glass substrate, it is difficult to obtain a clear image of the joint portion between the electrode and circuit pattern due to the state of the refraction of the glass substrate or the presence of the circuit pattern, although the outline of the semiconductor chip can be traced.
BRIEF SUMMARY OF THE INVENTION
Under these circumstances, the main object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of easily and accurately inspecting the bonding accuracy after a semiconductor chip is face-down bonded to a substrate.
Another object of the present invention is to provide a method of manufacturing a semiconductor device, capable of inspecting the alignment accuracy between a bump and a substrate by observation from outside without performing stripping or cutting of the device, after the face-down bonding.
In order to achieve the above-described objects, there is provided, according to the present invention, a method of bonding a semiconductor chip, comprising:
the step of photographing a surface of a semiconductor chip, on which an electrode is formed, and detecting a relative position of the electrode with respect to the semiconductor chip;
the bonding step of making the electrode of the semiconductor chip to face a circuit pattern provided on a substrate, and bonding the electrode to the circuit pattern;
the step of photographing the substrate on which the semiconductor chip is formed, and detecting a relative position of the semiconductor chip with respect to the substrate; and
the step of evaluating a bonding accuracy by calculating a relative position of the electrode with respect to the substrate from the relative position of the semiconductor chip with respect to the substrate and the relative position of the electrode with respect to the semiconductor chip.
In connection with the above method, it is preferable that the step of detecting the relative position of the electrode with respect to the semiconductor chip, should include photographing of the semiconductor chip from a surface side on which the electrode is formed, and detecting a position of the electrode with reference to a predetermined location of the semiconductor chip; and the step of detecting the relative position of the semiconductor chip with respect to the substrate, should include photographing of the semiconductor chip mounted on the substrate, from a surface side on which the electrode is not formed, and detecting the relative position of the predetermined location of the semiconductor chip, with reference to an alignment mark formed on the substrate as a reference.
With the above-described structure, the position of the electrode is detected with reference to a predetermined location of the semiconductor chip in advance to the bonding, and the relative position of the predetermined location of the semiconductor chip, with respect to the substrate is detected after the bonding. In this manner, the position of the electrode with respect to the substrate can be obtained by calculation. Therefore, it becomes possible to inspect the bonding accuracy without stripping the semiconductor chip from the substrate or cutting it.
Further, it is preferable that the predetermined location should be an edge of the semiconductor chip, especially a corner edge thereof. With this structure, it becomes unnecessary to provide a mark on the semiconductor chip.
It should be noted that the evaluation of the bonding accuracy should be carried out by comparing the relative position of the electrode with respect to the substrate with a predetermined reference value, and the reference value should be set by performing the teaching operation.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 3838274 (1974-09-01), Doubek, Jr. et al.
patent: 3946931 (1976-03-01), Bahnck et al.
patent: 4054386 (1977-10-01), Suzuki
patent: 4347964 (1982-09-01), Takasugi et al.
patent: 4671446 (1987-06-01), Sherman
patent: 4899921 (1990-02-01), Bendat et al.
patent: 5042709 (1991-08-01), Cina et al.
patent: 5092033 (1992-03-01), Nishiguchi et al.
patent: 5113565 (1992-05-01), Cipolla et al.
patent: 5212880 (1993-05-01), Nishiguchi et al.
patent: 5302854 (1994-04-01), Nishiguchi et al.
patent: 5342460 (1994-08-01), Hidese
patent: 5529236 (1996-06-01), Kobayashi
patent: 5590456 (1997-01-01), Armington et al.
patent: 5628660 (1997-05-01), Onitsuka
patent: 5680698 (1997-10-01), Armington et al.
patent: 5829125 (1998-11-01), Fujimoto et al.
patent: 5928399 (1999-07-01), Yakou et al.
patent: 362131528 (1987-06-01), None
patent: 362131529 (1987-06-01), None
patent: 405152794 (1993-06-01), None
patent: 5-251535 (1993-09-01), None
patent: 406244245 (1994-09-01), None
patent: 6-268050 (1994-09-01), None
patent: 6-310569 (1994-11-01), None
patent: 7-142545 (1995-06-01), None
patent: 8-078479 (1996-03-01), None
patent: 408330393 (1996
Ikeya Yukihiro
Kubo Tetsuya
Shibata Motojiro
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Ryan Patrick
Stoner Kiley
LandOfFree
Method for bonding semiconductor chip and device therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for bonding semiconductor chip and device therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for bonding semiconductor chip and device therefor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2561743