Method for blocking implants from the gate of an electronic...

Details Method for blocking implants from the gate of an electronic... Method for blocking implants from the gate of an electronic...

2002-08-05

2004-10-12

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S694000, C438S289000, C438S659000

Reexamination Certificate

active

06803315

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to forming a FET (Field Effect Transistor), and more particularly to a method of protecting the gate electrode of the FET from implants of unwanted impurities during implantation of regions of the FET. The FET is a Metal Insulator Semiconductor FET (MISFET) such as a Metal Oxide Semiconductor FET (MOSFET) where the insulator is an oxide and the “Metal” is a conductor such as doped polysilicon or a metal conductor.
2. Description of Related Art
U.S. Pat. No. 5,891,784 of Cheung et al. for “Transistor Fabrication Method” describes forming an anti-channeling hard mask in the form of an anti-channeling monolayer or a bilayer of doped silicon dioxide (BPSG or PSG), silicon nitride or silicon oxynitride between 100 Å and 4000 Å above a gate electrode stack, with no sidewall spacers having been formed when shallow junctions are being formed in the substrate. The anti-channeling hard mask can comprise a bilayer of undoped silicon oxide covered with doped silicon oxide or covered with silicon nitride. Alternatively an anti-channeling hard mask layer of doped silicon oxide may be progressively doped more heavily from bottom to top. The purpose is to prevent penetration of dopants through the gate electrode into the channel without protecting the gate electrode from the implanted dopant.
European patent application No. EP 0 771 021 of Chittipeddi et al. for “Transistor Fabrication Method” describes covering the gate electrode with a protective layer before ion implantation to prevent channeling. A protective oxide layer is formed on both the gate electrode stack and the substrate, but it is thicker on the gate electrode stack than on the substrate. The process uses differential oxidation to create a thicker silicon oxide layer on top of the polysilicon than on the underlying silicon to block implants from reaching the gate electrode, but will block them from reaching the extension also.
JP8097421A of Hiroshi et al for “Manufacture of Semiconductor Device” is directed to preventing the substrate of a device from being damaged during RIE, by performing a partial RIE after deposition of a silicon oxide spacer, implanting S/D and etching the rest of the silicon oxide. That process will not block the S/D implants from reaching the gate electrode.
U.S. patent application publication No. 2001/0011756 A1 of Yu for “Method for Forming Shallow Source/Drain Extension for MOS Transistor” performs implantation of an amorphization substance such as silicon or germanium into the substrate to form source and drain extensions under the gate in a process using a silicon oxynitride (SiO
x
N
y
) hard mask to prevent implantation of the gate. Then after the amorphization step, sidewall spacers are formed alongside the gate electrode. Next, dopant is implanted into the substrate to form S/D with the hard mask protecting the gate electrode using the silicon oxynitride (SiO
x
N
y
) hard mask again, to prevent implantation of the gate.
JP10-189959A of Horiuchi Katsutada for “Semiconductor Device” describes use of a hard mask and the gate electrode itself to block Arsenic (As) from reaching the substrate to prevent the substrate floating effect. Subsequently, there is a step of vertical ion implantation of Argon (Ar) followed by heat treatment to create a crystal defect region of polycrystals at the interface with an insulating film. The substrate floating effect can exist in an SOI-MOS structure in which a MOS transistor is formed on an insulating substrate or film in which the substrate region of the MOS transistor is floated. As the drain voltage rises, holes among pairs of electrons and holes generated by the impact ionization of channel carriers stay in the substrate region and bias the substrate region positive which causes the threshold voltage to drop, so the drain currents increase suddenly, rendering the potential of the substrate region of the SOI-MOS transistor unstable. This instability is referred to as the “substrate floating effect”. In addition, ionization is generated near the end portion of the drain region due to a small amount of the leakage current between the and drain.
U.S. Pat. No. 6,232,188 of Murtaza et al for “CMP-Free Disposable Gate Process” describes a disposable gate process which avoid use of Chemical Mechanical Polishing (CMP). A High Density Plasma Chemical Vapor Deposition (HDP-CVD) field dielectric composed of silicon oxide blocks implants from reaching S/D while leaving portions of the disposable gate exposed. The disposable gate is removed and then the gate electrode is deposited subsequently.
U.S. Pat. No. 6,118,161 of Chapman et al. for “Self-Aligned Trenched-Channel Lateral-Current-Flow Transistor” describes a disposable gate process in which source/drain (S/D) regions “may be implanted using the disposable gate as an implant block . . . ” Later the disposable gate is completely removed.
R. B. Fair, “Modeling Boron Diffusion in Ultrathin Nitrided Oxide p
+
Si Gate Technology”, IEEE Electron Device Lett., 18, 244 (1997) discusses thin gate dielectric materials, i.e. nitrided oxide films and the effects of fluorine and boron thereon.
M. Navi, and S. T. Dunham, Investigation of Boron Penetration Through Thin Gate Dielectrics Including Role of Nitrogen and Fluorine” J. Electrochem. Soc., 145, 2545 (1998).
SUMMARY OF THE INVENTION
The extension and source drain implants which also get implanted into the gate can cause problems for MIS/MOS devices. Thus, it is desirable to completely uncouple the gate implants from the extension and source drain implants of an FET device. For example, for a PFET, the extension implant regions and the source/drain implant regions can contain boron difluoride (BF
2
.) Boron difluoride (BF
2
) is amorphizing at the doses used in extension or S/D formation. Therefore the channeling of boron is reduced during a BF
2
implant. Boron diffusion is also suppressed during subsequent anneals because of the presence of fluorine in the extension implant regions and the source/drain implant regions. Therefore, it is easier to get ultra-shallow junctions with BF
2
than with boron alone. However, as the unwanted presence of fluorine in the gate electrode increases, there is an increasing problem of diffusion of extra fluorine from the BF
2
implant passing from the gate electrode through the gate dielectric into the underlying channel region. The extra fluorine from the BF
2
implant in the channel region is detrimental to MIS/MOS devices. It is well known that incorporation of fluorine into gate dielectric layers enhances boron diffusion in a process referred to as “boron penetration”. Boron penetration compromises the characteristics of gate dielectric layers and adversely affects the characteristics of the devices in which the condition of boron penetration exists. This is especially a big problem with ultra-thin silicon oxides (15 Å) and high-k_dielectrics that are currently being developed in the semiconductor industry. Accordingly, there is a need to protect the gate electrode from fluorine containing implants to prevent penetration thereof through the gate dielectric reaching the channel region (therebelow) in the substrate of the FET device.
Sometimes it is desirable to implant the S/D and/or extension region with a diffusion retarding species/element such as carbon in order to obtain ultra-shallow junctions. However, if carbon is introduced into a polysilicon gate electrode, dopant diffusion in the gate electrode can be suppressed. If the dopant does not diffuse to the bottom of the gate electrode, the resulting polysilicon depletion will be detrimental to the performance of the MOS device. For optimal device design, a polysilicon gate electrode must be protected from diffusion retarding species.
A polysilicon gate electrode is usually doped heavily to increase the polysilicon activation and minimize polysilicon depletion effects. If the S/D implant is also implanted into a polysilicon gate electrode, the dopant concentration reach a high enough conce

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