Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-04-18
2003-10-14
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S637000
Reexamination Certificate
active
06632742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a CMP process applied to the formation of a conductive wire by use of a damascene technique. In particular, the present invention relates to a method for avoiding the conductive wire from dishing and erosion effect produced during The CMP process.
2. Description of the Related Art
Chemical mechanical polishing (CMP) process is popularly applied to the planarization treatment of conductive wires in logic device processing and contact window processing. With respect to a damascene technique, after a contact window that passes through an insulating layer is filled with a conductive layer, the CMP process is utilized to remove the conductive layer outside the contact window, thus embedding the conductive layer into the insulating layer. However, during The CMP process, the stress transferred from a polishing pad to a chip is irregularly shared out when simultaneously polishing different materials or uneven portions. In general, when the insulating layer of a large area is employed as the polishing stop layer, a better polishing result is achieved. But, if an area ratio of the conductive wire to the insulating layer is over large, an over-polishing effect is produced.
The degree of the over-polishing effect depends on not only elasticity of the polishing pad and chemical characteristics of the polishing slurry, but also the pattern density and pattern size of the conductive wire. As shown in
FIG. 1
, when performing the CMP process on a conductive wire
2
of a high pattern density (more than 50%), the separated surface of an insulating layer
1
is very small and easily over-polished, and thus an appearance of erosion as shown by a dotted line
3
is produced in the insulating layer
1
. Referring to
FIG. 2
, when performing the CMP process on a conductive wire
5
of a large pattern area, polishing rates of the conductive wire
5
and an insulating layer
4
are different from each other, as a result, the center area of the conductive wire
5
presents severe dishing effects as shown by a dotted line
6
. Furthermore, it is noted that using a soft polishing pad of soft nature worsens the dishing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for avoiding erosion and dishing produced in the CMP process.
The method for avoiding defects produced in the CMP process of the present invention includes the steps of:
(a) providing a semiconductor substrate which has a plurality of predetermined contact window areas;
(b) sequentially depositing a first dielectric layer and a second dielectric layer on the semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer;
(c) performing a dry etching process to form a plurality of first holes on the plurality of the predetermined contact window areas respectively, wherein each of the first holes passes through the second dielectric layer and the first dielectric layer to a predetermined depth;
(d) performing the wet etching process to etch the first dielectric layer in each of the first holes until a predetermined width, and thereby a plurality of second holes are formed on the plurality of the predetermined contact window areas respectively;
(e) forming a conductive layer to fill each of the second holes; and
(f) performing the CMP process to level off the conductive layer and the second dielectric layer.
An advantage of the present invention is that the pattern density of the conductive layer disposed on the second dielectric layer is increased for resisting the transferred stress from the polishing pad and maintaining the shear stress of the conductive layer during the CMP process. Without changing the polishing pad, using different polishing slurries, tuning the polishing machine or improving the end-point detecting function, the present invention can effectively decrease erosion and dishing produced during the CMP process.
This and other objective of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5621241 (1997-04-01), Jain
patent: 5683922 (1997-11-01), Jeng et al.
patent: 6025277 (2000-02-01), Chen et al.
patent: 6197661 (2001-03-01), Mogami et al.
patent: 6355515 (2002-03-01), Moon et al.
Wang Jiun-Fang
Yang Ming-Cheng
Birch & Stewart Kolasch & Birch, LLP
Dang Phuc T.
ProMOS Technologies Inc.
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