Method for automatically generating test vectors for digital int

Details Method for automatically generating test vectors for digital int Method for automatically generating test vectors for digital int

1992-02-24

1994-12-27

Beausoliel, Jr., Robert W.

Excavating

371 223, G06F 1100, H04B 1700

Patent

active

053771974

ABSTRACT:
A sequential circuit test generation system and method to generate test patterns for sequential without assuming the use of scan techniques or a reset state utilizes the iterative logic array (ILA) model of the sequential circuit and a targeted-D propagation scheme employing both forward time processing (FTP) and reverse time processing (RTP) techniques for assigning a sequence of primary input (PI) values and for producing a an initial pseudo primary input (PPI) vector representing the initial state of the digital circuit at a particular time frame. Improved state justification techniques generate the remaining sequence of PI vectors necessary to put the circuit into the initial state from either known or don't care first states, by means of a heuristic method for reducing required initial state assignments. The method can also be applied to reduce the required number of PI vector assignments is also presented. In another phase of test vector generation, knowledge about the digital circuit behavior is obtained from a fault simulator to identify circuit nodes at which error signals are activated and partly propagated by already generated sequences of test vectors, and this knowledge is utilized with FTP techniques to generate test vector sequences for these nodes.

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