Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device
Reexamination Certificate
2003-03-28
2004-04-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
C257S190000, C257S018000, C438S478000, C438S758000
Reexamination Certificate
active
06724017
ABSTRACT:
TECHNICAL FIELD
The invention relates to an auto-organisation process for microstructures or nanostructures in a two-dimensional or three-dimensional lattice. It also relates to a device with auto-organised microstructures or nanostructures.
These microstructures or nanostructures are designed for making electronic, optical, opto-electronic or magnetic devices, and particularly Coulomb blocking devices using quantum dots.
STATE OF PRIOR ART
It is known that a microstructure or nanostructure arrangement on a surface can be determined using conventional photolithoetching methods. For example, a continuous layer of material chosen as a constituent of microstructures or nanostructures can be deposited on a surface. This may be a layer of silicon deposited by LPCVD. This layer is covered by a photosensitive film. After this film has been exposed, the geometries are recorded and are then transferred to the subjacent material. The state of the art is thus capable of defining nanostructures of the order of 20 nm. This is too large for target applications of the invention.
New methods, called “nano-printing”, are capable of defining nanometric structures, for example by deformation of a polymer with a mould. In this case also, the order of magnitude of structures thus defined is not easily less than 20 nm.
Techniques for material auto-organisation are also known by which nanostructures can be grown; growth on the edge of the steps of a vicinal surface, auto-organisation by dislocation lattices obtained during growth of metals, auto-organisation by dislocations during growth of different semiconducting layers. Auto-organisation is also possible by stacking nanostructures or by growing nanostructures on stressed surfaces with a variation in their topology due to relaxation of the internal stress. Impurities on the epitaxy surface can also be used. None of these techniques appears to make auto-organisation of nanostructures of nanometric size feasible with a good size uniformity.
It is also known that a crystalline nanostructure organisation can be obtained from a crystalline substrate on the surface of which a stress field was generated. Nanostructures can be obtained by selective treatment of the substrate and in this case the material forming the nanostructures is the same as for the substrate. They may also be obtained by epitaxial growth and in this case the crystalline substrate and the crystalline nanostructures are composed of materials that are different because they have different cell parameters.
Document FR-A-2 766 620 discloses a process for making microstructures or nanostructures on a support. The process comprises a step in which two wafers of crystalline material are brought into contact such that the crystalline lattices present on the faces of the wafers put into contact are offset by an angle enabling the formation of a lattice of crystalline defects within a crystalline zone close to the interface of the two wafers. A subsequent step to thin one of the two wafers reveals the microstructure or nanostructure on a support composed of the other wafer. The unthinned wafer may be an SOI substrate, for which the silicon surface film is brought into contact with the thinned wafer.
There are several problems inherent to these known processes.
A first problem is due to the fact that the nanostructures are in direct contact with the support substrate, even if the space between the nanostructures may be of different nature, and particularly different electrical nature, after appropriate treatment such as heat treatment. However, it may be useful to avoid current leaks between nanostructures and the support substrate. This type of leak makes the system unusable for controlling the transport of an electron from one nanostructure to another.
A second problem is the result of the fact that processes according to prior art require the generation of a stress field in the substrate, which limits the choice of the material from which the nanostructures are made. Cell parameters of the substrate and nanostructures must be compatible with the formation of nanostructures when the second material is deposited on the substrate. It is impossible to deposit nanostructures of the same nature as the substrate. For example, it would be very interesting to make silicon nanostructures on silicon substrates, since silicon is well known and is widely used in the microelectronics field.
A third problem relates to optimisation of nanostructure devices.
SUMMARY OF THE INVENTION
The invention proposes a solution to the problems described above. It relates to an auto-organisation process for microstructures or nanostructures in a two-dimensional or three-dimensional lattice, on an intermediate layer with a nature that may advantageously be different from the nature of the substrate. This intermediate layer is chosen so as to not hinder the organisation of nanostructures on the substrate. This arrangement is correlated to a stress field created on the surface of the substrate and transmitted through the intermediate layer as far as its surface. This arrangement of microstructures or nanostructures on the surface of the intermediate layer may in turn be used to organise one or several subsequent depositions of microstructures or nanostructures.
The invention is a means of independently choosing the substrate and the material from which nanostructures are composed.
The substrate is crystalline, single-material or composite. The intermediate layer may be crystalline or amorphous.
The nanostructures obtained according to the invention are in the form of a lattice of volumes with dimensions typically varying from one to several nanometers. These nanostructures may be made of a conducting, semiconducting or dielectric material with a crystalline or amorphous structure. For example, IV—IV compounds including Si, Ge, C, II-VI compounds, III-V compounds, Al
2
O
3
, SiO
2
and Si
3
N
4
, magnetic materials including Co, Ni, CoNi and semi-metallic materials such as Bi and NiMnSb may be used.
The invention enables the economical deposition of auto-organised nanostructures since the deposition is made in a single step over the entire surface. The dimensions of nanostructures vary from 1 nm to a few tens of nm.
The intermediate layer in the invention prevents any contamination of nanostructures by the substrate. Its function is firstly to facilitate putting nanostructures into order on the substrate and secondly to isolate nanostructures from the substrate.
Therefore, the purpose of the invention is a process for making microstructures or nanostructures on a support comprising the following steps:
a) supply of a substrate comprising at least one part composed of a crystalline material, this part having a surface with a stress field or a topology associated with the stress field, the stress field being associated with dislocations, the surface being adapted to the formation of a layer of material called the intermediate layer,
b) formation of the intermediate layer starting from said surface, the thickness and/or composition and/or a surface state of the intermediate layer being chosen such that the stress field can be transmitted through this layer as far as its free face that is suitable for the formation of microstructures or nanostructures, the substrate and the intermediate layer forming said support,
c) auto-organised deposition of microstructures and nanostructures on the free face of the intermediate layer.
Step a) may include bringing two wafers of crystalline material into contact such that the crystalline lattices formed on the faces of the wafers brought into contact are offset by an angle enabling the formation of a network of crystalline defects within a crystalline zone close to the interface of the two wafers, one of the wafers then being thinned to reveal said surface with a stress field or topology associated with a stress field.
Step a) may also include a surface treatment to adapt said surface to the formation of an intermediate layer.
The intermediate layer may be a layer deposited on said surface us
Baron Thierry
Eymery Hubert
Fournel Franck
Magnea Noël
Martin François
Commissariat a l'Energie Atomique
Crane Sara
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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