Method for automatic iterative area placement of module cells in

Details Method for automatic iterative area placement of module cells in Method for automatic iterative area placement of module cells in

1996-08-02

1998-12-08

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364491, G06F 1750

Patent

active

058479651

ABSTRACT:
In a computer system, a method for an area based place and route of an integrated circuit layout that provides automatic iterative area placement of module cells intelligently and effectively. In one embodiment, this is accomplished in three phases. The searching phase determines which hot spot is to be refined based on a congestion map. Next, the refining phase chooses a box with the proper aspect ratio, cut line direction, and placement options for minimizing the hot spot. The scheduling phase then decides whether to proceed with another area placement based on the current result or to restore a previous placement that exhibited superior characteristics. In the course of the area placements, several parameters are randomly varied in an intelligent manner so that successive iterative area placements produce equivalent or better results. All of this is accomplished without human intervention or expert knowledge. Instead, the computer system continuously runs its program until a design goal is attained.

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