Boots – shoes – and leggings
Patent
1996-04-26
1998-02-03
Louis-Jacques, Jacques
Boots, shoes, and leggings
364489, 364491, 364580, 371 221, 371 222, 39518301, 326 41, 326 46, 327211, 327213, G06F 1500, G01R 3128
Patent
active
057151725
ABSTRACT:
A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.
REFERENCES:
patent: T935003 (1975-06-01), Linville
patent: 4263651 (1981-04-01), Donath et al.
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5095454 (1992-03-01), Huang
patent: 5168455 (1992-12-01), Hooper
patent: 5210700 (1993-05-01), Tom
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5325309 (1994-06-01), Halaviati et al.
patent: 5345401 (1994-09-01), Tani
patent: 5416918 (1995-05-01), Gleason et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5475830 (1995-12-01), Chen et al.
patent: 5481695 (1996-01-01), Parks
patent: 5550748 (1996-08-01), Xiong
Malik et al: Retiming and resynthesis--Optimizing sequential networks with combinational techniques, IEEE, Oct. 1989.
Dey et al: Retiming sequential circuits to enhance testability, IEEE, Jun. 1994.
Chakraborty et al: Delay independent initialization of sequential circuits, IEEE, Jan. 1994.
Kahng et al., "High Performance Clock Routine Based on Recursive Geometric Matching," ACM/IEEE, 1991, pp. 322-327.
Louis-Jacques Jacques
Quickturn Design Systems Inc.
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