Electrical connectors – Aligning means for dual inline package
Reexamination Certificate
2005-05-24
2005-05-24
Duverne, J. F. (Department: 2839)
Electrical connectors
Aligning means for dual inline package
Reexamination Certificate
active
06896546
ABSTRACT:
A tip end of a stationary terminal section of a contact pin is inserted via a hole of a contact pin supporting plate into a common gap formed by holes, and held there the holes of the first position-restricting plate and the holes of the second position-restricting plate may be slid away from each other in a common plane to grip the end of the stationary terminal section of the contact terminal by the peripheral edges of the holes; the stationary terminal section of the contact terminal may have an engaging portion to be engageable with an open end peripheral edge of the hole in the first position-restricting plate.
REFERENCES:
patent: 3409861 (1968-11-01), Barnes et al.
patent: 3529213 (1970-09-01), Farrand et al.
patent: 4026412 (1977-05-01), Henson
patent: 4027935 (1977-06-01), Byrnes et al.
patent: 4622514 (1986-11-01), Lewis
patent: 4713022 (1987-12-01), Pfaff
patent: 4843315 (1989-06-01), Bayer et al.
patent: 5295841 (1994-03-01), Grabbe et al.
patent: 5397245 (1995-03-01), Roebuck et al.
patent: 63-255671 (1988-10-01), None
patent: 2000-113952 (2000-04-01), None
Ichihara Kenji
Shiratori Azusa
Duverne J. F.
Finnegan Henderson Farabow Garrett & Dunner LLP
Yamaichi Electronics Co. Ltd.
LandOfFree
Method for assembling semiconductor device socket does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for assembling semiconductor device socket, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for assembling semiconductor device socket will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3443045