Method for arranging logical cells in a semiconductor integrated

Details Method for arranging logical cells in a semiconductor integrated Method for arranging logical cells in a semiconductor integrated

1992-07-08

1995-03-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

364488, 364491, H01L 2100

Patent

active

053977491

ABSTRACT:
A method for arranging a group of logical cells through which a signal is transmitted within an allowable delay time, consisting of the steps of determining signal lines interconnecting the logical cells of the equipotential net, defining a critical path consisting of the signal lines of all the equipotential nets, classifying the logical cells positioned between the equipotential nets as path core cells and classifying the other logical cells as path branch cells, positioning the path core cells to shorten the length of a main signal route passing through the path core cells, positioning the path branch cells to shorten the distance between the main signal route and the path branch cell for each equipotential net, and decreasing the delay time of the critical path formed by the replaced path core cells and the replaced path branch cells within the allowable delay time.

REFERENCES:
patent: 5027353 (1991-06-01), Jarwala et al.
patent: 5155692 (1992-10-01), Lewandowski
patent: 5299139 (1994-03-01), Baisuck et al.
"Chip Layout Optimization Using Critical Path Weighting," Proc. 21st DAC, pp. 133-136, 1984, A. E. Dunlop, et al.
"Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's", Proc. 23rd DAC. pp. 404-410, 1986, Y. Ogawa, et al.
"A Fast Algorithm for Performance-Driven Placement", Proc. ICCAD, pp. 328-331, 1990, Michael A. B. Jackson, et al.

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