Patent
1989-10-05
1991-06-11
Carroll, J.
357 45, 357 54, 357 71, H01L 2968, H01L 2710, H01L 2934, H01L 2348
Patent
active
050236814
ABSTRACT:
A method for arranging EEPROM cells and a semiconductor device manufactured by the method is disclosed. The semiconductor device with an EEPROM cell arrangement comprises a plurality of segmentized buried diffusion regions formed on a semiconductor substrate with each segmentized buried diffusion region with a diffusion region formed in the semiconductor substrate between a selecting transistor and a buried diffusion region and with a diffusion region formed in the semiconductor substrate between adjacent segmentized buried diffusion regions with a contact formed on each diffusion region to connect the diffusion region to a first conducting layer for resistance reduction. The selecting transistor connects the segmentized buried diffusion regions to a bit line through a first conduction layer for via contact and a second conducting layer for bit line by selecting a predetermined number of segmentized buried diffusion regions. Preferably, the method for arranging EEPROM cells includes a column of erased cells between the predetermined number of bit lines, thereby protecting an overcurrent from flowing in the word line direction when a bit line is selected.
REFERENCES:
patent: 4686558 (1987-08-01), Adam
patent: 4707457 (1987-11-01), Erb
Carroll J.
Hyundai Electronics Industries Co,. Ltd.
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