Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-04-13
2001-01-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06181599
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to non-volatile semiconductor memories, and more particularly, to methods and structures for reducing the disturbance of threshold voltages when writing to such memories.
2. Description of Related Art
Non-volatile semiconductor memories such as EPROMs, EEPROMs, and Flash memories are well known. In such memories, a threshold voltage Vt of a memory cell indicates a data value stored in the memory cell. When writing (programming) to a selected memory cell in a conventional non-volatile memory array, programming voltages are applied via a word-line (WL) connected to a control gate of the selected cell, via a bit-line (BL) connected to a drain of the selected cell, and a via a source-line (SL) coupled to a source of the selected cell. The combination of programming voltages changes the threshold voltage of the selected cell, typically by causing Fowler-Nordheim (F-N) tunneling or channel hot electron (CHE) injection which charges (or discharges) a floating gate in the selected memory cell.
For example, to induce CHE injection in a selected memory cell containing a typical n-channel floating gate transistor, a high voltage Vpp (e.g., approximately 9 to 12 volts or higher) is applied as the control gate voltage Vg to the WL containing the selected cell, a high voltage (e.g., approximately 4.5 to 5.5 volts or higher) is applied as the drain voltage Vd to the BL containing the selected cell, and a low voltage (e.g., near 0 volt) is applied as the source voltage Vs to the SLs. Hot electrons are injected into the floating gate to increase the threshold level with respect to the control gate, thereby programming the selected cell. By adjusting the magnitude and/or duration of the programming voltage Vpp, the selected cell can be programmed to a desired threshold voltage Vt.
During a write to a selected memory cell, the high bit-line and word-line voltages for the selected memory cell can create large voltage differences between the floating gate and drain of unselected memory cells and thereby induce Fowler-Nordheim tunneling that disturbs the threshold voltages of these unselected memory cells by causing electrons to tunnel out or escape from the floating gate to drain. The voltage difference between the drain and floating gate of an unselected memory cell subjects the memory cell to a disturb typically referred to program or drain disturb. Since the Fowler-Nordheim tunneling current is exponentially dependent on the electric field in the gate oxide between the bit-line and floating gate, program disturb will worsen significantly even with a small increase in the electric field. If this F-N tunneling current is high enough for a long enough time, the threshold voltages of previously programmed cells can be lowered significantly, thereby adversely affecting the accuracy of the storage array.
The disturbance of threshold voltages can accumulate through repeated programming of memory cells in the same column or row and change the data values stored in unselected cells. Depending on the memory, a data value stored in a memory cell may be binary (a bit 0 or 1), multi-level (a value from a set of discrete values), or analog (a value within a continuous range of possible values). For binary memories, the accumulated disturbance of a threshold voltage must be relatively large (on the order of a volt or more) to change the threshold voltage from a state indicating a first binary value to a state indicating the second binary value. However, for multi-level or analog memories, distinguishable threshold voltage differences for data values can be a few millivolts, and any small disturbances of threshold voltages limit the theoretically achievable threshold voltage resolution.
The total accumulative disturb is dependent on the number of cells on a bit-line, the write time of a cell, the area and gate oxide thickness between the drain and the floating gate, and the drain voltage applied for programming. Thus, program disturb can limit, among other things, the number of cells that are allowed on a single bit-line, as well as the thickness of the gate dielectric of the memory cells. On the other hand, reducing bit-line lengths decreases program disturb. For example, a large array can be divided into several smaller arrays so that fewer memory cells are on the same row or column. As a result, programming a selected memory cell disturbs fewer unselected memory cells, and the accumulated programming disturb time for each memory cell is less. For example, dividing a large array into four small arrays can divide bit-line and word-line lengths in half and reduce accumulation of threshold voltage disturbance in half. However, four small arrays have about twice the overhead in decoding circuitry, as does one large array containing the same number of memory cells, which increases the cost and size of the memory system.
Accordingly, it is desired to reduce program disturb without the adverse effects of conventional methods and memories discussed above.
SUMMARY
In accordance with an aspect of the invention, applying a variable bias voltage to control gates of unselected memory cells containing data values (i.e., previously programmed cells) reduces program disturb. The amount of bias voltage applied depends on the threshold voltage of the unselected programmed memory cell. The bias voltage increases the voltage of the floating gate (making the floating gate voltage less negative) through capacitive coupling between the control gate and the floating gate and thus reduces the voltage difference between the floating gate and the drain in memory cells in the same column as a selected memory cell being programmed. The bias voltage reduces the electric field in the gate oxide, which reduces program disturb to the corresponding floating gate.
The bias voltage is only applied to word-lines of rows which currently hold data values, but not to the unselected memory cells which are in the erased state so that erased memory cells remain off during programming. Application of a bias voltage to erased memory cells is not required because a small disturbance of the threshold voltage of an erased cell does not affect data values or operation of the memory. Furthermore, the applied bias voltage is higher for unselected programmed memory cells having higher threshold voltages, resulting in a greater decrease in the electric field of these memory cells, which further reduces program disturb in the memory array.
In one embodiment of the present invention, a bias voltage Vbias1 is applied to unselected word-lines during programming if memory cells in the word-line have programmed threshold voltages at or above a reference voltage Vref1. However, if the unselected word-line contains memory cells with programmed threshold voltages below reference voltage Vref1 or memory cells that are erased, a ground potential is applied to these word-lines during subsequent programming of other word-lines. In another embodiment, an additional bias voltage Vbias2, whose value is between ground and Vbias1, can be applied to unselected programmed memory cells during programming of cells in other word-lines. In this case, if the programmed threshold voltage of the cell in the selected bit-line is less than reference voltage Vref1, but at or above a reference voltage Vref2 associated with Vbias2, then Vref2 is applied to the unselected programmed memory cells. If the programmed threshold voltage is below Vref2 or the cells are erased, then ground is applied, and if the programmed threshold voltage is at or above Vref1, bias voltage Vref1 is applied to the unselected programmed memory cells.
In yet another embodiment, two different non-zero bias voltages Vbias1 and Vbias2 are applied to unselected programmed memory cells, depending on whether the programmed threshold voltage of the cell on the selected bit-line is above or below a predetermined reference voltage Vref1. If the threshold voltage is at or above reference voltage Vref1, the higher of the two bias voltages Vbias1 is applied t
Majestic, Parsons, Siebert & Hsue
Phan Trong
SanDisk Corporation
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