Method for anodizing a polysilicon layer lower capacitor plate o

Details Method for anodizing a polysilicon layer lower capacitor plate o Method for anodizing a polysilicon layer lower capacitor plate o

1991-05-06

1991-11-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, 357 236, H01L 2170

Patent

active

050681990

ABSTRACT:
A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated pores in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated pores in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.

REFERENCES:
Fazan et al., "Electrical Characterization of Textured Interpolycapacitors for Advanced Stacked DRAMs", IEDM, 1990, pp. 663-666.
Mine et al., "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs", Extended Abstracts of the 21st Conference of Solid State Devices and Materials, Aug. 89, Tokyo, pp. 137-140.
M. I. J. Beale, N. G. Chew, M. J. Uren, A. G. Cullis, and J. D. Benjamin; "Microstructure and Formation Mechanism of Pourous Silicon;" Jan. 1, 1985, Appl. Phys. Lett., pp. 86-88.

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