Method for and a trailing store buffer for use in memory...

Details Method for and a trailing store buffer for use in memory... Method for and a trailing store buffer for use in memory...

2003-12-23

2009-12-29

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

Reexamination Certificate

active

07640419

ABSTRACT:
Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient memory renaming. The method includes computing a store address, writing the store address in a first storage, writing data associated with the store address to a memory, and de-allocating the store address from the first storage, allocating the store address in a second storage, predicting a load instruction to be memory renamed, computing a load store source index, computing a load address, disambiguating the memory renamed load instruction, and retiring the memory renamed load instruction, if the store instruction is still allocated in at least one of the first storage and the second storage and should have effectively provided to the load the full data. The method may also include re-executing the load instruction without memory renaming, if the store instruction is not in at the first storage or in the second storage.

REFERENCES:
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patent: 6918030 (2005-07-01), Johnson

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