Method for analyzing voltage fluctuations in multilayered electr

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364485, G01R 3130

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active

055660835

ABSTRACT:
The present invention features a method for analyzing voltage fluctuations in multilayered electronic packaging structures. A physical electronic packaging structure having at least two, spaced-apart, metallic planes and a via are first provided. This package has an inherent input impedance associated with the via and is essentially dependent upon the radius of the via. A numerical model of a portion of the physical electronic packaging structure containing the via is made. An effective input impedance of the numerical model is then obtained. A unique impedance transforming operation is used to cause the effective input impedance of the numerical model to essentially match the input impedance of the physical structure, thus allowing an accurate simulation of the physical structure.

REFERENCES:
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patent: 5221858 (1993-06-01), Higgins, III
Equivalent Circuit Models Of Via Interconnections In Eltronics Packaging, IEEE 1994.
Electrical Performance Of Electronic Packaging, IEEE Nov. 2, 1994.
1994 IEEE Multi-Chip Module Conference MCMC-94, IEEE Mar. 15, 1994.
Model Of Interaction Between Signal Vias And Metal Planes In Elect. Packaging, IEEE 1994.
Modeling Of Power/Ground Plane Noise In High Speed Digital Elect. Packaging, IEEE 1993.

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