Method for analyzing electrical contact between two...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C324S765010, C324S755090, C324S1540PB

Reexamination Certificate

active

06172513

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a diagnosing technology for semiconductor devices and, more particularly, to a method for analyzing a contact between an electrode and a conductive layer incorporated in a semiconductor device without destruction thereof.
DESCRIPTION OF THE RELATED ART
Various kinds of contact are incorporated in semiconductor devices. These kinds of contact are broken down into two categories. The first category is called an ohmic contact, and exhibits a low resistance against electric current. The second category exhibits abrupt current-to-voltage characteristics, and typical examples are known as a Schottky junction and a p-n junction.
The contact in the second category is, by way of example, used for a gate electrode of a field effect transistor. The structure and operating principle of an field effect transistor will be explained with reference to
FIG. 1
, which is a top view of a heterojunction field effect transistor. Parallel to the plane of the figure, a Schottky barrier layer
1
of GaAlAs is provided over a heterojunction between an electron supply layer of GaAlAs and a channel layer of InGaAs, and is covered with a contact layer
3
of GaAs. A gate recess
4
is formed by removing the contact layer
3
, exposing the Schottky barrier layer
1
. A gate electrode
5
of Ti/Au/Pt alloy is formed in the gate recess
4
on the Schottky barrier layer
1
. A source electrode
6
of AuGe/Au alloy and a drain electrode
7
of AuGe/Au alloy are provided on both sides of the gate electrode
5
, and are electrically connected to the channel layer. By applying appropriate voltage bias to the gate, electrical current between the source electrode
6
and the drain electrode
7
can be switched on and off.
Various reasons for analyzing contacts and methods of doing so in the prior art will be illustrated, using the gate contact as an example.
In operation, an electrical current, known as gate current, flows between the gate electrode and source or drain electrodes. This gate current degrades performance, and the manufacturer must control production so that the gate current lies within user specifications.
FIG. 2
illustrates the gate current as a function of bias voltage between gate and source electrodes. The solid line R
1
represents the gate current of a product which meets user specifications. The dashed line D
1
represents the gate current of a product which is defective, because the gate current exceeds user specifications. In the latter case, the manufacturer must analyze the product to ascertain the cause of high gate current, and arrange future production so that the gate current is within specifications.
In the prior art, scanning electron microscopy is a typical method of analysis. In scanning electron microscopy, the product is cleaved and observed in cross section, as illustrated in
FIG. 3
, which is a cross section of a defective product taken along line A—A of FIG.
1
. Although the source/ drain electrodes
6
/
7
are not shown in
FIG. 3
, the heterojunction, the Schottky barrier layer and the contact layer are labeled with the same references, and other references
8
,
9
,
10
and
11
designate a substrate of GaAs, a buffer layer of GaAlAs, the channel layer of InGaAs and the electron supply layer of GaAlAs, respectively. If, as shown in
FIG. 3
, the gate recess
4
is too narrow to space the gate electrode
5
from the contact layer
3
, the gate electrode
5
is brought into contact with the contact layer
3
, leakage current flows from the gate electrode
5
to the contact layer
3
, and the gate current is varied along the dotted line D
1
. The manufacturer must then arrange future production so that the gate electrode
5
is not brought into contact with the contact layer
3
.
Another prior art method of analysis is secondary ion mass spectroscopy. Secondary ion mass spectroscopy measures the concentration of elements in the product.
FIG. 4
illustrates the actual aluminum and silicon concentration as a function of depth from the upper surface of a defective product, measured by secondary ion mass spectroscopy. In addition, the silicon concentration is designed as indicated by plots PL
1
. The design silicon concentration is low in the Schottky barrier layer
1
from depth D
1
to depth D
2
, and is high in the electron supply layer
11
from depth D
2
to depth D
3
. The actual aluminum concentration is increased between depth D
1
to depth D
3
, i.e., in both Schottky barrier and electron supply layers
1
/
11
. However, the actual silicon concentration is increased in the Schottky barrier layer
1
. The large silicon concentration in the Schottky barrier layer
1
is causative of high gate current as indicated by dotted line D
1
. Thus, there are various origins of unusual bias voltage-to-gate current characteristics, and the manufacturer ascertains the origin through the analysis of the contact.
Another reason for the analysis of a contact is to influence of a design change. For example, in order to increase the operating frequency of a circuit, the circuit designer typically replaces the field effect transistor with one of shorter gate length. However, the remainder of the circuit must be redesigned appropriately for the new field effect transistor. However, redesign is not possible until the characteristics of the new field effect transistor are known. The circuit designer can wait until the new field effect transistor is fabricated, and measure the characteristics. However, methods which can predict the characteristics before fabrication result in a savings of time.
In addition, the dimensions of a gate electrode may be unintentionally changed. For example, if the kind of photo-resist used in gate fabrication is found to be undesirable from the aspect of environment, the manufacture changes the photo-resist to another kind of photo-resist. The new photo-resist may be different in pattern transfer characteristics from the previous photo-resist. This means that the new photo-resist unintentionally changes the dimensions of the gate electrode. When the manufacturer wants to maintain the original dimensions of the gate electrode, the manufacturer is required to change the parameters of the photo-lithography. In the prior art, the manufacturer carefully determines the parameters of the photo-lithography, using the scanning electron microscope to measure the gate length.
Thus, the manufacturer evaluates the voltage-to-current characteristics of an electrode by using a testing system, and observes the microstructure of the electrode through the scanning electron microscope and the secondary ion mass spectroscopy. The testing system, the scanning electron microscope and the secondary ion mass spectroscopy are useful for the manufacturer. However, those apparatus are expensive, and the analysis requires a large amount of time and labor. Moreover, the product is to be broken before the observation through the scanning electron microscope and the secondary ion mass spectroscope. The manufacture can not freely analyze products of the semiconductor device. A non-destructive analyzing method is desirable.
A non-destructive analyzing method is disclosed by, for example, Hiraoka et. al. in IEEE Transactions on Electron Devices, vol. ED-34, No. 4, April 1987, page 721. This prior art non-destructive analyzing method-is hereinbelow described with reference to
FIGS. 5 and 6
.
FIG. 5
is a top view of an n-p-n bipolar transistor, and
FIG. 6
is a circuit schematic of the same. The n-p-n bipolar transistor is assumed to have an emitter contact
21
, a base contact
22
and a collector contact
23
. Though not shown in
FIG. 5
, a base region is formed in a collector region, and an emitter region is nested in the base region. An emitter electrode
24
, a base electrode
25
and a collector electrode
26
are held in contact with the emitter region, the base region and the collector region, respectively, and the emitter contact
21
, the base contact
22
and the collector contact
23
are formed between the emitter region and th

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for analyzing electrical contact between two... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for analyzing electrical contact between two..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for analyzing electrical contact between two... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2539347

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.