Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2003-08-11
2004-12-07
Thai, Luan (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06828776
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method for analyzing process parameters, and more particularly, to a method for analyzing defect inspection parameters.
2. Description of the Prior Art
In a semiconductor manufacturing technique, many processes, such as the photolithography processes, the etching processes, and the ion implantation processes are required to complete the fabrication of a semiconductor product. That means a large number of equipment and complicated procedures are utilized in a semiconductor manufacturing process. Therefore, those of ordinary skill in the art are concentrated on ensuring the proper operation of equipment, sustaining or improving production yield rate, detecting and verifying problems, and periodically maintaining facilities for production, etc, so as to maintain the company's operation in good progress and produce products having good quality.
In order to identify the semiconductor processing problems, the following data, such as the process parameter data, the in-line quality control (in-line QC) data, the defect inspection data, the sample test data, the wafer test data, and the final test data, are analyzed. The defect inspection data is acquired by inspecting the defects in each layer on the wafer. The defect inspection data includes the total count of defects, the adder count of defects, and the class count of defects. The data obtained from defect inspection is usually represented by a defect distribution map.
Please refer to FIG.
1
.
FIG. 1
is a flow chart of a prior art method for analyzing defect inspection parameters. As shown in
FIG. 1
, step
101
is first executed by those of ordinary skill in the art to perform inspection according to various defect inspection items to each wafer. For example, the total count of defects in an intermetal dielectric layer is inspected.
Step
102
is thereafter executed to find out the products having abnormal defect inspection results by reviewing the results of each defect inspection item of each wafer. Please refer to FIG.
2
.
FIG. 2
is a schematic diagram of a defect inspection parameter distribution map for a wafer. As shown in
FIG. 2
, a wafer is divided into a plurality of dies
21
. A plurality of black dots represent the sites of defects
22
occurring in a specific layer on the wafer.
In step
103
, those of ordinary skill in the art determine the possibly faulty process step according to personal experience and the defect distribution maps of abnormal products obtained from step
102
. For example, the possibly faulty process step may be a process step for forming a polysilicon layer, a metal layer, an intermetal dielectric layer, etc.
Finally, those of ordinary skill in the art find out the ill-functioned equipment by checking the equipment utilized in the process step determined in step
103
. For example, those of ordinary skill in the art judge that the products are out of spec according to the total count of defects in the intermetal dielectric layer first, then determine the possibly faulty process step to be the intermetal dielectric layer deposition process step, and eventually find out the ill-functioned equipment, such as the depositing equipment, the etching equipment, etc.
Since the analysis results are determined according to humans experience (step
103
) in the prior art, the accuracy and the confidence level of the final analysis results are open to question. Furthermore, the human affairs in semiconductor manufacturing change frequently. Engineer's personal experience is difficult to transfer. The capacity of each engineer is limited, meaning the engineer is unable to look after the operation status of all of the equipment. When the defect inspection results indicate abnormalities, it is thus difficult for engineers, lacking in experience, to judge which point causes the problem to occur. Therefore, a lot of time is consumed to do related research, and even worse, wrong decisions are made. This will not only reduce the efficiency of processes, but also increase the cost, Furthermore, the in-line production status can not be improved in time to increase yield rate.
It is therefore very important to provide an analytical-method to rapidly and correctly judge which point causes the problem to occur when the defect inspection data of semiconductor products indicates abnormalities.
SUMMARY OF INVENTION
It is a primary objective of the claimed invention to provide a method for analyzing defect inspection parameters to rapidly and correctly judge which point causes the problem to occur when the defect inspection data of semiconductor products indicates abnormalities.
It is another primary objective of the claimed invention to provide a method for analyzing defect inspection parameters to revise the kill ratio of the defect inspection according to the results of defect inspection and wafer test.
It is a feature of the claimed invention to utilize the commonality analysis means to analyze defect inspection parameters by coordinating with the database recording each defect inspection item and correlated processing equipment.
The claimed invention method for analyzing defect inspection parameters are utilized for analyzing a plurality of lots of products. Each of the plurality of lots of products has a lot number. The plurality of lots of products are fabricated through a plurality of manufacturing equipment. At least one wafer in each of the plurality of lots of products is inspected according to at least one defect inspection item to generate at least one defect inspection parameter. The defect inspection item, the defect inspection parameter, and a process step correlated to the defect inspection item are stored in a database. The method includes: searching for the defect inspection parameters of the plurality of lots of products from the database, classifying the plurality of lots of products into at least a qualified group and a failed group according to the defect inspection parameters, searching for the process step correlated to the defect inspection item from the database, searching for the manufacturing equipment through which the qualified group has passed in the process step and the manufacturing equipment through which the failed group has passed in the process step, and determining the manufacturing equipment through which the probability that the failed group has passed which is greater than that of the qualified group.
Each wafer of each lot of products is tested according to a wafer test item correlated to the defect inspection item to generate a wafer test parameter. The wafer test item and the wafer test parameter are stored in the database. The present invention method for analyzing defect inspection parameters utilizes the overlapping means to compare the wafer test parameter distribution map and the defect distribution map to find out optimum kill ratio of the defect inspection.
It is an advantage of the claimed invention to utilize the commonality analysis means to analyze the defect inspection parameters by coordinating with the database recording each defect inspection item and related processing equipment. Therefore, the point causing the problem to occur is judged rapidly and correctly to find out the ill-functioned equipment when the defect inspection data of semiconductor products indicates abnormalities. Furthermore, the kill ratio of the defect inspection is revised according to the results of defect inspection and wafer test to avoid mistakes incurred from human's judgment, leading to higher processing efficiency, lower cost, and better in-line production status control to increase yield rate.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 4618938 (1986-10-01), Sandland et al.
patent: 5761064 (1998-06-01), La et al.
patent: 6016562 (2000-01-01), Miyazaki et
Luo Haw-Jyue
Tai Hung-En
Hollington Jermele
Hsu Winston
Powerchip Semiconductor Corp.
Thai Luan
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