Amplifiers – With amplifier condition indicating or testing means
Patent
1997-06-12
1998-05-05
Mottola, Steven
Amplifiers
With amplifier condition indicating or testing means
330129, H03G 330
Patent
active
057480389
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a power amplifier, such as an amplifier employing closed loop feedback (e.g. Cartesian feedback) and it specifically relates to linearisation of such power amplifier.
BACKGROUND TO THE INVENTION
Linear transmitters are well known. To achieve both linearity and efficiency in such devices linearisation techniques are employed in a power amplifier such as a Cartesian feedback loop. A Cartesian feedback loop is a closed loop negative feedback technique which sums the baseband feedback signal in it's I and Q formats to I and Q input signals prior to amplifying and up-converting the signal to its output frequency and power level.
New digital linear technologies require highly linear amplification which cannot be achieved through conventional transmitter design Meanwhile, limited spectrum resources are continually forcing the development of spectrally efficient linear power transmitters. The restrictions on out-of-band emissions are severe (-60 dBc to -70 dBc). Furthermore, operating efficiency of the amplifiers must also be maximised.
U.S. Pat. No. 5,066,923 to Motorola, Inc. describes a training scheme of linear power amplifiers in which a high degree of linearity is achieved and maintained through amplifier trig efforts performed over short periods of time. The training must be accomplished before the transmitter operates in normal transmitting mode. The training effort comprises of phase and amplitude training periods. Phase training is used in order to secure the stability in the closed loop amplifier operation while amplitude training is responsible for a level set-up of input signal hence preventing amplifier non-linearity due to excessive levels of the driving signal.
One method of amplitude training includes increasing the voltage of an input test signal over a period of time reaching levels high enough to drive the power amplifier into saturation. Differential voltage at the output of a summation point is used as a measure of amplifier linearity. The level of the input signal that makes the differential voltage go above a predefined threshold is detected and known as the clipping point. During transmission the amplitude range of a message signal is maintained below dipping point thus ensuring amplifier operation in linear range. Thus, when properly adjusted such power amplifiers operate in a satisfactorily linear mode.
A disadvantage of the above described training method is that during training the ramping up of the input training signal does not stop after clipping point is reached, in fact, the ramp up continues past clipping point causing the power amplifier to splatter. In other words, the training input signal ramps up for a period of time in which the threshold voltage is exceeded causing undesired adjacent channel interference.
It is desired to have method of amplitude training for a power amplifier where the input training signal does not exceed clipping point thereby minimising the amount of adjacent channel interference.
SUMMARY OF THE INVENTION
A method is provided for determining an optimum operating point in a linear power amplifier by adaptively changing an input training signal of a feedback circuit.
A first embodiment of the present invention includes adaptively changing the input training signal by iteratively changing a parameter of a feedback circuit thereby performing multiple iterations of the feedback circuit during a training period.
The parameters that may be iteratively changed are the time duration of each iteration (sequence) and the magnitude of the input training signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a linear transmitter according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a linear transmitter according to a second embodiment of the present invention.
FIG. 3 is a differential voltage graph resulting from employing the embodiments of FIGS. 1 or 2.
FIG. 4 shows multiple iteration sequences for the embodiments of FIGS. 1 or 2.
FIG. 5 shows multiple iter
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patent: 5041793 (1991-08-01), Gailus
patent: 5376895 (1994-12-01), Aihara
patent: 5467055 (1995-11-01), Wray et al.
patent: 5469105 (1995-11-01), Sparks
patent: 5524285 (1996-06-01), Wray et al.
Bastani Babak
Boscovic Dragan
Valentine Stephen
Wray Anthony
Egan Wayne J.
Motorola Inc.
Mottola Steven
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