Method for amorphous silicon local interconnect etch

Details Method for amorphous silicon local interconnect etch Method for amorphous silicon local interconnect etch

2000-06-01

2002-03-19

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Optical characteristic sensed

C438S006000, C438S007000, C438S008000, C438S706000, C438S710000, C438S714000, C216S060000

Reexamination Certificate

active

06358760

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of manufacturing a semiconductor device. The present invention has particular applicability in manufacturing high density semiconductor devices using local interconnect conductors.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration semiconductor devices require submicron features, increased transistor and circuit speeds and high reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and multiple dielectric and conductive layers formed thereon. An integrated circuit is formed containing multiple conductive patterns comprising conductive lines separated by interwiring spacings, and multiple interconnect lines, such as bus lines, bit lines, word lines and local interconnect lines.
As device features continue to shrink in size, the local interconnect lines enable the semiconductor device to offer more packing density, higher speeds and more flexibility in circuit design. In conventional local interconnect methodology, amorphous silicon may be deposited over titanium. The amorphous silicon may then be patterned with a local interconnect resist mask. Subsequently, the amorphous silicon areas that are not covered by the resist mask are etched away using an amorphous silicon etch. A high temperature rapid thermal anneal (RTA) follows to form a titanium silicide local interconnect conductor.
A consistent and precise etching of the amorphous silicon layer is essential for predictable device performance. For example, incomplete etching leaves an amorphous silicon residue over the semiconductor device that may subsequently cause device failures due to electrical shorts. Additionally, over etching may cause the loss of amorphous silicon that is to be used to form the titanium silicide local interconnect conductor. This may result in a higher resistance for the local interconnect conductor, thereby lowering the device speed. Over etching may also unintentionally cause the loss of titanium formed beneath the amorphous silicon layer. This unintentional loss of titanium may adversely impact the formation of a titanium silicide layer at the surface of the source/drain regions.
Conventional processes for etching amorphous silicon employ a plasma etching chamber using fluorine-based reactants and a fixed time etch. For example, according to conventional methodology, CF
4
and N
2
may be used to plasma etch amorphous silicon for a predetermined period of time, based on the thickness of the amorphous silicon layer. Conventionally, the CF
4
is provided at a flow rate of about 140 standard cubic centimeters per minute (sccm) and the N
2
is provided at a flow rate of about 25 sccm. Additionally, the pressure in the etching chamber in conventional fixed time etching processes is maintained at about 800 milliTorr (mT). One drawback with such conventional fixed time etching processes is that the etch rate and film variations make it very difficult to achieve a precise etch. As a result, the end product after etching often yields inconsistent results. That is, the semiconductor device may suffer from over etching on some occasions while on other occasions, the semiconductor device may suffer from under etching.
Another drawback with conventional amorphous silicon etching is that a heavy polymer forms in the plasma etching chamber during etching. These polymers significantly change the etching chamber conditions. As the number of wafers processed in the chamber increases, the polymer built up in the chamber will progressively slow down the amorphous silicon etch rate. Accordingly, amorphous silicon residues are often seen from wafer to wafer because of inefficient etching caused by the decreased etch rate. Additionally, the polymers themselves often leave residues on the semiconductor devices after the etching. Conventional methods to clean the post-etch polymer residues are often ineffective in cleaning the residues without attacking the underlying titanium.
DISCLOSURE OF THE INVENTION
There exists a need for methodology that eliminates the problems associated with etching amorphous silicon.
These and other needs are met by the present invention, where a plasma etching device is used to etch an amorphous silicon layer formed over a titanium layer. The plasma etching device uses an endpoint detector to detect when the amorphous silicon not covered by a resist mask has been completely etched. A titanium silicide interconnect may then be formed by annealing the semiconductor device.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method for etching a semiconductor device in a plasma etching chamber. The semiconductor device includes a silicon layer formed over a titanium layer. The method includes providing CF
4
and N
2
into the plasma etching chamber. The method also includes etching the semiconductor device in the plasma etching chamber and monitoring optical emissions from the plasma etching chamber. The method further includes terminating the etching when an intensity of the optical emissions reaches a predetermined level.
According to another aspect of the invention, a method for manufacturing a semiconductor device is provided. The method includes forming a dielectric layer on an upper surface of a semiconductor substrate, forming a gate electrode on the dielectric layer and sequentially depositing a titanium layer and a silicon layer over the gate electrode. The method also includes forming a mask over predetermined portions of the silicon layer, the predetermined portions defining a local interconnect line. The method further includes etching the silicon layer in a plasma etching chamber, monitoring optical emissions from the plasma etching chamber and terminating the etching when an intensity of the optical emissions reaches a predetermined level.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 5413950 (1995-05-01), Chen et al.
patent: 5728253 (1998-03-01), Saito et al.
patent: 5989928 (1999-11-01), Nakata et al.

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