Method for alleviating the step difference in a semiconductor an

Details Method for alleviating the step difference in a semiconductor an Method for alleviating the step difference in a semiconductor an

1991-11-21

1994-01-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

257649, 437 52, H01L 2144

Patent

active

052815552

ABSTRACT:
A method of diminishing a step difference 41 in a multi-layered semiconductor device which comprises determining a location 40 of a step difference 41 on a multi-layered semiconductor device 50 to be formed by utilizing a plurality of conducting layers 35 and a plurality of insulating layers 36 sequentially formed such that the layers are sequentially stacked on a surface of a substrate to form a step difference 41 location 40 on the substrate is disclosed. A conducting layer 3 is deposited on the substrate. A first dummy layer 3C is formed at the step difference location while simultaneously forming a gate electrode 3A and a gate electrode line 3B by performing a mask patterning process. A first insulating layer 5 is deposited on the gate electrode 3A, gate electrode line 3 and the first dummy insulating layer 5A. A second conducting layer 6 is deposited on the first insulating layer 5. A second dummy layer 6B, having a predetermined size to diminish the step difference at the step difference location is formed while simultaneously forming a charge storage electrode 6A by performing a mask patterning process. A second insulating layer 9 is deposited on the resulting structure such that the step difference is diminished to permit overlying layers deposited at the location of the now diminished step difference to be removed without forming a stringer. A semiconductor device which includes the dummy layers is also disclosed.

REFERENCES:
patent: 4617730 (1986-10-01), Geldermans et al.
patent: 4916514 (1990-04-01), Nowak
patent: 4949162 (1990-08-01), Tamaki et al.
patent: 5032890 (1991-07-01), Ushika et al.
patent: 5060045 (1991-10-01), Owada et al.

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