Method for aligning shallow trench isolation

Details Method for aligning shallow trench isolation Method for aligning shallow trench isolation

1998-12-30

1999-09-07

Arroyo, Teresa M.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438427, 438975, 148DIG102, H01L 2176

Patent

active

059500930

ABSTRACT:
A method for aliging a shallow trench isolation is provided. An aligning mark which is deeper than a prior technique is formed in a provided substrate. A trench is formed and an aligning trench is formed in the position over the aligning mark. A thick oxide layer is deposited on the semiconiductol substrate, in the trench and in the aligning trench. After a portion of the thick oxide layer removed, another portion of the thick oxide layer is removed by etching back. A gate oxide layer is formed on a substrate comprising the trench and the aligning trench. A polysilicon layer with the step-height profile in the position over the aligning mark is formed on the gate oxide layer.

REFERENCES:
patent: 5536675 (1996-07-01), Bohr
patent: 5733801 (1998-03-01), Gojohbori
patent: 5786260 (1998-07-01), Jang et al.
patent: 5893744 (1999-04-01), Wang

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