Method for aligning a serial bit stream with a parallel output

Details Method for aligning a serial bit stream with a parallel output Method for aligning a serial bit stream with a parallel output

2011-01-25

2011-01-25

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C714S718000

Reexamination Certificate

active

07876244

ABSTRACT:
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.

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International Search Report for PCT/IB2010/052376 dated Sep. 29, 2010; 7 pages.

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