Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2005-02-22
2005-02-22
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C430S312000, C257SE21522
Reexamination Certificate
active
06858445
ABSTRACT:
The present invention provides a method for optimizing the overlay adjustment of two mask planes in a photolithographic process for the production of an integrated circuit having the following steps: provision of a substrate (S) with at least one first mask plane (ME), which has been patterned by exposure of a first mask using a first exposure device; orientation of a second mask (M), which is provided for the patterning of a second mask plane using a second exposure device, with respect to the first mask plane (ME); measurement of the overlay between the first mask plane (ME) and the second mask (M); analysis of the measured overlay taking account of error data (FAD, FXD, FBD, FYD) provided, in advance regarding errors (FA, FX, FB, FY) of the first and second masks and/or errors of the first and second exposure devices; carrying out of a correction of the orientation of the second mask (M) depending on the result of the analysis.
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Progler, Christopher, et al.,Method to Budget and Optimize Total Device Overlay, Partt of the SPIE Conference on Optical Microlithography XII, Santa Clara, California, Mar. 1999, pp. 193-207.
Armitage, Jr., John D.,Analysis of Overlay Distortion Patterns, SPIE vol. 921, Integrated Circuit Metrology, Inspection, and Process Control II (1988), pp. 207-222.
Brinks Hofer Gilson & Lione
Fourson George
Infineon - Technologies AG
Pham Thanh V
LandOfFree
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