Method for adjusting the leakage current of silicon-on-sapphire

Metal working – Method of mechanical manufacture – Assembling or joining

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29574, 29590, H01L 1114

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active

040915271

ABSTRACT:
A method for adjusting the leakage current of insulated gate field effect transistors comprised of silicon mesas epitaxially formed on a sapphire substrate, wherein the leakage current of a P channel transistor is increased by preoxidizing the silicon prior to standard processing and/or wherein the leakage current is decreased by annealing the silicon in a reducing atmosphere in addition to standard processing steps. The leakage current of an N channel transistor is reduced by preoxidizing the silicon of the transistor prior to forming the transistor and/or is increased by annealing in a reducing atmosphere in addition to the steps necessary for forming the transistor.

REFERENCES:
patent: 3867196 (1975-02-01), Richman
patent: 3885993 (1975-05-01), Tihanyi
patent: 3958266 (1976-05-01), Athanas
patent: 3974560 (1976-08-01), Mueller et al.
Allison et al.; Thin-Film Silicon:Preparation, Properties, & Device Applications; pp. 1490-1498; Proceedings of the IEEE, vol. 57, No. 9, Sep. 1969.
Heiman; Thin-Film Silicon-on-Sapphire Deep Depletion MOS Transistors; pp. 855-862, IEEE Transactions on Electron Devices, vol. Ed-13, No. 12, Dec. 1966.

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