Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-08-11
2003-04-08
Patel, Ramesh (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S117000, C700S120000, C700S150000, C700S157000, C700S155000, C700S160000, C438S624000, C438S632000, C438S690000, C438S763000, C451S008000, C451S010000, C451S022000, C451S041000
Reexamination Certificate
active
06546306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to the field of semiconductor processing, and, more particularly, to polishing operations in semiconductor processing operations.
2. Description of the Related Art
Chemical mechanical polishing (“CMP”) is widely used in semiconductor processing operations as a means of planarizing various process layers, e.g., silicon dioxide, formed above a wafer comprised of a semiconducting material, such as silicon. Chemical mechanical polishing operations typically employ an abrasive slurry distributed in an alkaline or acidic solution to planarize the surface of a process layer through a combination of mechanical and chemical actions.
The continual drive to reduce feature sizes, e.g., channel length, on semiconductor devices has increased the importance of chemical mechanical polishing or planarization in the semiconductor fabrication process. For example, as feature sizes tend to decrease, the depth of field of photolithography equipment tends to shrink, thereby necessitating a very flat or planar surface so that very small dimensions may be accurately patterned on a wafer. Additionally, there has been, and continues to be, a constant drive to increase the productivity of fabrication techniques employed in making modern semiconductor devices. In short, there is a constant drive within the industry to make the same high-quality semiconductor products, but to do it faster, better, and in a less expensive manner.
FIG. 1
is a schematic drawing of one illustrative embodiment of a chemical mechanical polishing tool used in semiconductor processing operations. As depicted therein, the illustrative polishing tool
10
is comprised of a rotatable table
12
on which an illustrative polishing pad
14
is mounted, and a multi-head carrier
16
positioned above the pad
14
. The multi-head carrier
16
includes a plurality of rotatable polishing arms
18
, each of which includes a carrier head
20
. Typically, wafers (not shown) are secured to the carrier heads
20
by the use of vacuum pressure. This is sometimes referred to as the carrier backforce pressure. In use, the table
12
is rotated and an abrasive slurry is dispensed onto the polishing pad
14
. Once the slurry has been applied to the polishing pad
14
, a downforce is applied to each rotating polishing arm
18
to press its respective wafer against the polishing pad
14
. As the wafer is pressed against the polishing pad
14
, the surface of the process layer on the wafer is mechanically and chemically polished. Although the tool depicted in FIG. is a multi-head polishing tool
10
, similar single-head type machines exist in the industry, and the present invention is not limited to any particular embodiment, form or structure of a tool that may be used to perform chemical mechanical polishing operations.
In general, wafers are polished according to various polishing recipes that may vary, depending upon a variety of factors, e.g., the type of material being polished, the desired rate of removal of the product, etc. Ideally, after polishing operations are performed, the surface of a process layer will be precisely planar. However, in the practice, this ideal situation may not be attained. For example, as shown in
FIG. 2
, a surface
31
of a process layer
32
formed above a semiconducting substrate
30
may be convex, i.e., bulged in the middle area of the process layer. This domed-type topography is often referred to as a center-slow or edge-fast polishing profile because the center region
15
of the process layer
32
polishes at a slower rate than the edge region
17
of the process layer
32
. Alternatively, after some polishing operations, as shown in
FIG. 3
, a surface
33
of a process layer
32
formed above a semiconducting substrate
30
may be concave, i.e., dished at the center region of the process layer. This situation is sometimes referred to as a center-fast or edge-slow polishing profile. This occurs when the polishing rate at the center region
15
of the process layer
32
is greater than the polishing rate at the edge region
17
of the process layer
32
.
Such illustrative variations across a surface of a process layer after polishing operations may be due, in part, to the inherent nature of polishing operations. Moreover, the variations may be combined, i.e., convex surfaces in given areas and concave surfaces in others across the surface of the wafer. Simply put, after traditional polishing operations, the surface of the process layer is not as uniform as would otherwise be desired for efficient processing operations.
The present invention is directed to a method of solving, or at least reducing, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method for compensating for thickness variations in process layers subjected to planarization operations. In one illustrative embodiment, the method comprises determining a polishing profile produced by a polishing tool and manufacturing a process layer with a surface profile prior to polishing operations based upon the determined polishing profile of the polishing tool. In another illustrative embodiment, the method comprises determining variations in the thickness of a first process layer after polishing operations are performed on the first process layer, and varying the manufactured thickness of a second process layer prior to performing polishing operations on the second process layer. the manufactured thickness of the second process layer being based upon the determined thickness variations in the first process layer.
REFERENCES:
patent: 5851846 (1998-12-01), Matsui et al.
patent: 6135859 (2000-10-01), Tietz
patent: 6150274 (2000-11-01), Liou et al.
patent: 6151532 (2000-11-01), Barone et al.
patent: 6179709 (2001-01-01), Redeker et al.
patent: 6213848 (2001-04-01), Campbell et al.
patent: 6230069 (2001-05-01), Campbell et al.
patent: 6265314 (2001-07-01), Black et al.
Bushman Scott
Campbell William Jarrett
Patel Ramesh
Williams Morgan & Amerson P.C.
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