Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
2002-07-03
2004-10-19
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S311000, C430S330000, C356S496000, C356S636000
Reexamination Certificate
active
06806008
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for adjusting a temperature in a resist process after the exposure of at least one semiconductor wafer.
With continuously decreasing feature sizes in semiconductor wafer manufacturing, the influence with respect to accuracy of detail processes other than exposure on a lithographic track are growing more and more important.
The sequence of detail process steps on a lithographic track typically starts with depositing an adhesive substance, e.g. HMDS (hexamethyl disilazane), followed by coating the semiconductor wafer with a resist having a thickness of 0.3-5 &mgr;m, depending on the technology used. After stripping the resist off of the backside and the edges of the wafer, a prebake step with a temperature of, e.g., 80-100° C. is applied to the wafer for improving the adhesion and for hardening the resist.
After prebake—also called softbake—the exposure of the photo sensitive resist with a pattern projected from a mask or reticle in a wafer stepper or scanner is performed.
A resist process is then started by applying a post-exposure bake with typical temperatures of 100-110° C., which is intended to generate a small flow of resist for smoothing out periodic intensity modulation due to interference effects. Those are produced by a possible back-reflection from a layer that underlies the resist layer and results in generating stationary waves.
In a development step, chemically altered resist material—due to a photo-chemical reaction—is removed in case of a positive photo resist, thereby leaving behind a pattern structure in the resist layer.
In order to increase the resistance of the photo resist layer against the following etching step depending on its aggressivity, a temperature of about 120° C. is applied to the resist for a third time known as the post-bake step. This step may be replaced by UV-hardening.
When using a chemically amplified resist, the temperatures applied may considerably deviate from the values given above. Chemically amplified resists are often used for an exposure wave length of 248 nm and below.
The final processes are etching, thereby transferring the resist pattern into the desired layer, or implantation followed by stripping off the resist. As is clearly visible from the process steps described, the temperature treatment is a critical issue on the lithographic track. Typically, there are small temperature windows with a lower temperature limit given by, e.g. a glassy point for which the desired function of the resist becomes active, and an upper limit at which plastic resist flow sets in. Further requirements are the reduction of water absorption and adhesion improvement.
Unfortunately, particularly the upper limit of the temperature represents a smooth limit and the disadvantageous effect of resist flow may already become apparent at moderate temperatures, e.g. during post-exposure bake, if particularly small feature sizes will be patterned into the resist.
Investigations related to quantifying this effect on line shapes can be found, e.g., in “Selective modification of resist sidewall profiles with a post development bake”, IBM Technical Disclosure Bulletin, Vol. 32, 1989, pages 141-145, XP 000049332, wherein line shape profiles are measured as a function of post exposure bake temperature. In addition, reference can be made to Young-Soo Sohn et al., “Effect of temperature variation during post exposure bake on 193 nm chemically amplified resist simulation”, Digest of papers Microprocesses and Nanotechnology, 2000, Society of Applied Physics, Japan, XP 001051557, which describes the performance of critical dimension measurements of lines structured in a resist, which have each experienced different temperatures.
Moreover, processes are adapted to fixed values of the temperature setup and in order to maintain uniformity from wafer to wafer, temperature deviations have to be particularly small, e.g. below 1° C.
In order to improve the temperature treatment of the different baking steps, a system for uniform heating of a photo resist is provided in U.S. Pat. No. 6,034,771. In this teaching, radiation is applied to the photo resist, and an actual temperature of the resist can be determined from a measurement of the reflected light. Given this temperature information, a deviation from a desired value can be calculated and a temperature adjustment can be performed using heating lamps that irradiate heating light onto the resist. The temperature is thereby determined indirectly from a relationship between, e.g. resist thickness and temperature, or resist absorption and temperature, which has to be known a priori.
Unfortunately, it is not clear whether such a relationship remains constant during the different processing steps, thereby providing sufficient accuracy to adjust the temperature.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for adjusting the temperature in a resist process which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
It is a primary objective of the present invention to improve the temperatures during different baking steps in a resist process in order to adhere to wafer specification tolerances, and to thereby improve the wafer yield on the lithographic track.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for adjusting a temperature in a resist process. The method includes: providing at least a first semiconductor wafer coated with a resist; and providing a reticle test pattern including at least one pad structure having a first critical dimension and at least one antenna structure having a second critical dimension. The antenna structure is connected to the pad structure and the first critical dimension is at least 1.5 times the second critical dimension. The method also includes: exposing the first semiconductor wafer by projecting the pattern onto the resist to configure the pattern into the resist; performing a first resist process on the first semiconductor wafer while applying a first temperature; and determining a first sidewall angle of the pattern in the resist on the first semiconductor wafer by:
a) obtaining a first measured value by measuring the second critical dimension of the antenna structure,
b) obtaining a second measured value by measuring the first critical dimension of the pad structure, and
c) comparing the first measured value and the second measured value.
The method then includes: issuing a first signal, if the first sidewall angle exceeds a pre-defined threshold value; and adjusting the temperature of the resist process in response to the first signal.
In accordance with an added feature of the invention, the method includes: providing at least a second semiconductor wafer coated with a resist; exposing the second semiconductor wafer to configure the pattern in the resist on the second semiconductor wafer; performing a second resist process on the second semiconductor wafer with a second temperature that is different from the first temperature; measuring a second sidewall angle of the pattern in the resist on the second semiconductor wafer; comparing the first sidewall angle and the second sidewall angle; issuing a second signal, if the difference between the first sidewall angle and the second sidewall angle exceeds a pre-defined difference threshold value; and adjusting the temperature of the resist process in response to the second signal.
In accordance with an additional feature of the invention, the the pattern in the resist on the first semiconductor wafer is structured within a scribeline area of the first semiconductor wafer; and the pattern in the resist on the second semiconductor wafer is structured within a scribeline area of the second semiconductor wafer.
In accordance with another feature of the invention, the step of determining the first sidewall angle is performed by using a scanning electron microscope, an interferometer, and/or a scatterometer.
In other wor
Schedel Thorsten
Seidel Torsten
Duda Kathleen
Greenberg Laurence A.
Infineon Technologies SC300 GmbH & Co. KG
Locher Ralph E.
Stemer Werner H.
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