Method for adaptive critical path delay estimation during...

Details Method for adaptive critical path delay estimation during... Method for adaptive critical path delay estimation during...

2006-11-07

2006-11-07

Rodriquez, Paul L. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07133819

ABSTRACT:
Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.

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