Method for achieving uniform etch depth using ion...

Details Method for achieving uniform etch depth using ion... Method for achieving uniform etch depth using ion...

2006-06-16

2009-02-24

Tran, Binh X (Department: 1792)

Semiconductor device manufacturing: process

Chemical etching

Altering etchability of substrate region by compositional or...

C438S719000, C438S723000, C438S743000

Reexamination Certificate

active

07494933

ABSTRACT:
A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

REFERENCES:
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patent: 2003/0216044 (2003-11-01), Lin et al.
Mathew et al., “Inverted T Channel FET (ITFET)—Fabrication And Characteristics Of Vertical-Horizontal, Thin Body, Multi-Gate, Multi-Orientation Devices, ITFET SRAM Bit-Cell Operation. A Novel Technology For 45nm And Beyond CMOS”, 2005 IEEE, 4 pgs.
North et al., “Tapered Windows In Phosphorus-Doped SiO2 By Ion Implantation”, 1978 IEEE, IEEE Transactions On Electron Devices, vol. ED-25, No. 7, Jul. 1978, pp. 809-812.
Lauwers et al., “CMOS Integration Of Dual Work Function Phase Controlled Ni FUSI With Simultaneous Silicidation Of NMOS (NiSi) And PMOS (Ni-rich silicide) Gates On HfSiON”, 2005 IEEE, 4 pgs.

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