Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-07-26
2002-11-19
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S763010, C714S733000
Reexamination Certificate
active
06483337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor structures, and more particularly, to a method for characterizing latchup parameters of semiconductor structures.
2. Discussion of the Related Art
In bulk CMOS structure, a phenomenon known is latchup can occur, which will now be described with reference to
FIGS. 1 and 2
. As shown in
FIG. 1
, a typical bulk CMOS structure includes a P substrate having an N well formed therein. The P substrate forms part of an NPN MOS transistor
12
, while the N well forms part of a complementary PNP MOS transistor
10
, all as is well-known. The P region of the MOS transistor
10
, N well, P substrate and P region in P substrate form a PNP parasitic bipolar transistor Q
1
, we the N well, N region in N well, P substrate and N region of the MOS transistor
12
form an NPN parasitic bipolar transistor Q
2
. The equivalent circuit including the two parasitic bipolar transistors Q
1
, Q
2
, substrate resistance Rsub and N well resistance R well are shown in FIG.
2
.
Latchup can occur when Vout drops below Ground due to, for example, a noise spike. With Vout connected to the base of the parasitic bipolar NPN transistor Q
2
, sufficient current may flow through Rsub to turn on parasitic bipolar transistor Q
2
. This will draw current through R well, which will turn on transistor Q
1
, so that a self sustaining low resistance path between power rails is formed. If the gains of the transistors Q
1
and Q
2
are such that &bgr;
1
of transistor Q
1
times &bgr;
2
of transistor Q
2
is greater than 1, latchup can occur. Once latchup has begun, the only way to stop it is to reduce the current below a critical level, usually by removing power from the circuit.
Typically, latchup characterization of a product consists of an initialization process which uses appropriate test vectors to tristate all outputs and put the devices in a known, stable state at maximum power supply voltage. Then, a constant current is superimposed to a single input (a “trigger”) for, for example 1 millisecond The power supply current is measured a few milliseconds later, to see if a high current state is retained after the trigger is removed, which would indicate device latchup. Typically, each input is triggered in incremental fashion up to the pass/fail limit, for example 100 milliamps. Clearly this methodology is very slow for a high leadcount package and throughput depends strongly upon the number of steps to reach the pass/fail trigger current. But in reality a latchup event is likely to preclude any further testing of any additional inputs, and is likely to preclude pushing the existing input further.
Therefore, what is needed is a method for achieving a test which yield data about the latchup characteristics of devices, which test can be performed quickly and which is non-destructive to the devices.
SUMMARY OF THE INVENTION
In the present invention, a semiconductor structure is tested for latchup characteristics by imposing currents of increasing levels on the semiconductor structure. The current change in the structure is measured upon imposition of each such level of current, and it is noted when any imposition in current on the semiconductor structure results in a corresponding current change in the structure which is not substantially linearly proportional to the amount of current imposed thereon, thereby gaining knowledge of the latchup characteristics of the structure. Other structures are tested in the same manner, and the measurements taken with regard to these structures are compared to gain knowledge of the latchup characteristics of the structures.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 3768011 (1973-10-01), Swain
patent: 4797724 (1989-01-01), Bolder
patent: 4939616 (1990-07-01), Rountree
patent: 5225702 (1993-07-01), Chatterjee
patent: 5528188 (1996-06-01), Au
Blish Richard C.
Johnson Scott E.
Advanced Micro Devices , Inc.
Nguyen Trung
Sherry Michael
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