Method for accessing banks of DRAM

Details Method for accessing banks of DRAM Method for accessing banks of DRAM

1999-06-01

2001-10-02

Lee, Michael (Department: 2714)

Television

Image signal processing circuitry specific to television

With details of static storage device

C348S718000, C345S520000, C345S519000, C711S005000

Reexamination Certificate

active

06297857

ABSTRACT:

REFERENCE TO RELATED APPLICATIONS
This application is related to British Patent Application entitled “Method for Accessing Banks of DRAM” as U.K. Serial No. 9415391.3 filed on Jul. 29, 1994 and British Patent Application entitled “Video Decompression” as U.K. Serial No. 9405914.4 filed on Mar. 24, 1994 and British Patent Application entitled “Method and Apparatus for Interfacing with RAM” as U.K. Serial No. (not yet known) filed on Feb. 28, 1995.
BACKGROUND
This invention relates to Random Access Memory (RAM), and more particularly, to a method for accessing different banks of dynamic RAM. One of the most popular types of RAM is Dynamic Random Access Memory (DRAM). Much attention has been paid to methods for accessing (reading from or writing to) DRAMs. The main concern is speed of access. The dominant limitation on access speed is the need to precharge the RAM before starting an access.
Access speed is greatly increased by accessing more of the RAM using a single precharge, a technique called page mode addressing. In page mode addressing, a block of data words (two or more) has the same row address for each word. Accessing the block involves charging only the column addresses of the data words in the block, not the fixed row address, thus saving on the need to precharge before continuing the access.
Refreshing and precharging in a timely and efficient manner is accomplished by interleaving blocks of data into two separate banks of DRAMS. In this manner, while one DRAM bank is being accessed, the other bank could be safely refreshed or precharged, thereby eliminating (or at least reducing) dead time. Ideally, data would be accessed from the one bank in blocks long enough that refreshing or precharging of the other bank could be finished. In practice, however, this does not always occur because RAM memory systems typically lack a provision for selecting which particular bank to refresh.
These two methods can be combined, as disclosed in U.S. Pat. No. 5,274,788. This patent discloses a RAM memory system in which contiguous memory address locations are interleaved, on a single page basis, between two DRAM banks.
While the combined technique of '788 patent is generally adequate, it is most effective when handling access to a linear sequence of data blocks that are read cut of DRAM in essentially the same order as they were written into the DRAM (e.g., cache memory systems). In some applications, however, data blocks are actually related to each other in two (or more) dimensions (e.g., digital video). There is therefore a need for a memory system that interleaves between banks in a manner that takes into account the multi-dimensional relationship between the data blocks.
SUMMARY OF THE INVENTION
This invention discloses a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image. The DRAM includes two separate banks, a first bank and a second bank. Each bank is capable of operating in page mode to read and write the data words. The two dimensional image is organized in a two dimensional grid pattern of cells, each cell containing an M by N matrix of pixels. The words associated with each cell occupy, one page or less of a bank. Each cell is assigned a particular one of the two banks so that all data words associated with that particular cell are read from and written to one particular page of that particular bank. The assignment of banks to cells is done such that each cell is associated with a different bank than any bordering cell which is also either in the same row or in the same column. There is then read the data words associated with a cell that is composed of a matrix of pixels, and that is not aligned with the two dimensional grid pattern, but that is aligned with pixels in cells in the two dimensional grid pattern.
In accordance with another aspect of the invention, the data words associated with the unaligned cell are read by first reading; from the first bank of DRAM, the data words associated with one of the cells in the grid pattern identified as containing data words associated with the unaligned cell. Then there are read, from the second bank of DRAM, the data words associated with another of the cells in the grid pattern containing data words associated with the unaligned cell. Alternate readings between the first and second banks are continued until all the data words associated with the unaligned cell have been read.
In accordance with another aspect of the invention, the data words associated with the unaligned cell are read by first reading, in a predetermined order of cells, the data words associated with each cell in the grid pattern containing data words associated with the unaligned cell. The predetermined order of cells is chosen such that data words read from succeeding cells are read from alternating banks.
In accordance with another aspect of the invention, the predetermined order is a clockwise rotation of cells in the grid pattern identified as containing data words associated with the unaligned cell. Alternately, the predetermined order is a counter-clockwise rotation of cells in the grid pattern identified as containing data words associated with the unaligned cell.


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