Patent
1995-10-18
1998-01-06
Lall, Parshotam S.
G06F 938
Patent
active
057064890
ABSTRACT:
A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU do the rest of the operation synchronously, or c) resume the parallel operation in the processor or a hardware assist if an interruption caused the PIE-PF parallel operation to be checkpointed.
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Chi Chi-Hung
Ghafir Hatem Mohamed
Iyer Balakrishna Raghavendra
Narang Inderpal Singh
Rao Gururaj Seshagiri
Coulter Kenneth R.
Ehrlich Marc A.
Goldman Bernard M.
International Business Machines - Corporation
Lall Parshotam S.
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