Abrading – Precision device or process - or with condition responsive... – By optical sensor
Reexamination Certificate
2000-10-25
2003-02-11
Hail, III, Joseph J. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
By optical sensor
C451S285000
Reexamination Certificate
active
06517413
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of determining when the endpoint of a copper Chemical Mechanical Polishing process has been reached.
(2) Description of the Prior Art
One major aspect of creating semiconductor devices is the aspect of creating surfaces of near ideal planarity or flatness. This requires polishing of semiconductor surfaces with the objective of removing unwanted particles from the surface.
It is well known in the art that forming semiconductor devices requires a large number of complex interrelated processing steps to form particular device features, these processing steps typically use and depend on a flat surface. The creation of semiconductor devices further frequently requires the creation of these devices in a number of overlaying layers of material, which further complicates the required processing steps since planarity must be maintained from layer to layer within the device structure. Good surface planarity is critically important to lithography processes since these processes depend on maintaining depth of focus. Two common techniques used to achieve planarity on a semiconductor surface are a Spin-On-Glass (SOG) etchback process and a Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the surface of the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The motion of the wafer relative to the polishing pad creates abrasive action. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals which comprise an insulating layer of the wafer, while the size of the silicon dioxide particles controls the physical abrasion of the surface of the wafer. The polishing of the wafer is accomplished when the silicon dioxide particles abrade away the oxidized chemicals. An important parameter during the polishing operation is the polishing efficiency, which is the amount of material that is removed from the surface of the substrate by the CMP process as a function of time. This efficiency is, among others, dependent on the density of the pattern or the concentration of the raised areas on the surface that is being polished.
During the CMP process, the allocated polishing time and the downforce exerted on a wafer that is being polished are typically fixed and independent of the topography of the surface that is being polished. The removal rate of material from a wafer has been shown to be directly proportional to the downward force exerted on the surface that is being polished and inversely proportional to the surface area that comes into contact with the polishing pad. The removal rate of material therefore increases as the size of the polished surface decreases, and visa versa. Since different integrated circuits have different surface topographies, the material removed during a CMP process may vary from substrate to substrate and between various layers within a device structure.
Because dimensions of Integrated Circuit (IC) devices in advanced IC's continue to decrease, the dimensions of conductors and interconnection elements, which connect and interconnect those integrated circuit devices, also continue to decrease. Dimensions of conductor and interconnection elements, which directly contact IC devices, have typically decreased the greatest, thus becoming the smallest in dimension of conductor and interconnecting elements in advanced IC's. These narrow conductors and interconnections typically comprise the first conductor or interconnection level, which contacts an integrated circuit device. First conductor levels have traditionally been formed from aluminum metal or aluminum metal alloys. First interconnection levels (i.e. first conductive contact studs) are typically formed using tungsten. Conducting lines in the era of micron and sub-micron device features must have a high level of conductivity while simultaneously showing limited susceptibility to degradative phenomenon such as electromigration, a requirement that grows in importance as wire widths decrease. Electromigration may, under extremely high current densities, result in an electrical open and is most common in aluminum metal and aluminum metal alloy conductor and interconnect elements and has not typically been observed in interconnects made of tungsten. Although copper and copper alloys possess the high electrical conductivity and low electromigration susceptibility desired for conductor elements and interconnection elements within advanced IC's, methods through which copper and copper metal alloys may be formed into conductor and interconnection elements within advanced IC's are neither well developed nor well understood.
Thus, in this regard, aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than other better conductors such as copper, gold, and silver. Copper does provide the advantages of improved conductivity and reliability, but does as yet provide a challenge where a layer of copper must be etched using conventional methods of photolithography and reactive ion etching (RIE). This is due to the fact that copper does not readily form volatile species during the process of RIE. To circumvent these problems, other methods of creating interconnect lines using copper have been proposed such as depositing the copper patterns using methods of Chemical Vapor Deposition (CVD) or selective electroless plating. The composition of the deposited layer of metal, if the preferred element contained in the layer of metal is copper, can be changed by the addition of other metallic substances in order to improve deposition results. Copper has only recently gained more attention as an interconnect metal. Copper is known for its relatively low cost and low resistivity, copper however also has a relatively large diffusion coefficient into surrounding dielectrics such as silicon dioxide and silicon. Copper has the additional disadvantage of being readily oxidized at relatively low temperatures, therefore conventional photoresist processing cannot be used because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment. Copper from an electrical interconnect may diffuse into a surrounding layer of dielectric (such as a layer of silicon dioxide), causing the dielectric to become conductive while at the same time decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier layer in order to prevent diffusion into the surrounding silicon dioxide layer. Silicon nitride can serve as a diffusion barrier to copper, but prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon di
Hu Tien-Chen
Lu Chen-Fa
Twu Jin-Churng
Ackerman Stephen B.
Hail III Joseph J.
Ojini Anthony
Saile George O.
Taiwan Semiconductor Manufacturing Company
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